Quotables
"I hate what they've done to my child...I would never let my own children watch it. "
Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7928008 | Method for fabricating semiconductor device A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on. The method for fabricating the semiconductor device includes the steps of: forming a transistor included in the semiconduct... | 04/19/2011 |
| 7833902 | Semiconductor device and method of fabricating the same In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insula... | 11/16/2010 |
| 7531451 | SIP semiconductor device and method for manufacturing the same A System In Package (SIP) semiconductor device and a method for manufacturing a SIP device. A TiSiN film may be used as a diffusion barrier film for metal wiring in a SIP semiconductor device. A TiSiN film may provide relatively good step coverage in a relatively ea... | 05/12/2009 |
| 7442319 | Poly etch without separate oxide decap The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a hi... | 10/28/2008 |
| 7427543 | Method to improve drive current by increasing the effective area of an electrode The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 | 09/23/2008 |
| 7372105 | Semiconductor device with power supply impurity region A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing... | 05/13/2008 |
| 7358181 | Method for structuring a semiconductor device A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts... | 04/15/2008 |
| 7351654 | Semiconductor device and method for producing the same A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon... | 04/01/2008 |
| 7348265 | Semiconductor device having a silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located ov... | 03/25/2008 |
| 7329596 | Method for tuning epitaxial growth by interfacial doping and structure including same A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that r... | 02/12/2008 |
| 7291527 | Work function control of metals Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first... | 11/06/2007 |
| 7265038 | Method for forming a multi-layer seed layer for improved Cu ECP A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator... | 09/04/2007 |
| 7253052 | Method for forming a storage cell capacitor compatible with high dielectric constant materials Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion o... | 08/07/2007 |
| 7245015 | Display apparatus In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the displa... | 07/17/2007 |
| 7238612 | Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconduc... | 07/03/2007 |
| 7232745 | Body capacitor for SOI memory description A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between th... | 06/19/2007 |
| 7202143 | Low temperature production of large-grain polycrystalline semiconductors An oxide or nitride layer is provided on an amorphous semiconductor layer prior to performing metal-induced crystallization of the semiconductor layer. The oxide or nitride layer facilitates conversion of the amorphous material into large grain polycrystalline mater... | 04/10/2007 |
| 7195995 | Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area ... | 03/27/2007 |
| 7189641 | Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on ... | 03/13/2007 |
| 7169696 | Method for making a system for selecting one wire from a plurality of wires A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionall... | 01/30/2007 |
| 7162796 | Method of making an interposer with contact structures A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads substantially as close as desired to the body of the chip package.... | 01/16/2007 |
| 7163017 | Polysilicon etch useful during the manufacture of a semiconductor device A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is forme... | 01/16/2007 |
| 7163880 | Gate stack and gate stack etch sequence for metal gate integration The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes depositing a metal layer (210) over a gate dielectric layer (215) located over a ... | 01/16/2007 |
| 7160801 | Integrated circuit using a dual poly process A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrysta... | 01/09/2007 |
| 7160811 | Laminated silicate glass layer etch stop method for fabricating microelectronic product A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned sali... | 01/09/2007 |
| 7144807 | Low resistivity titanium silicide on heavily doped semiconductor Low resistivity, C54-phase TiSi2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about... | 12/05/2006 |
| 7125803 | Reverse tone mask method for post-CMP elimination of copper overburden A novel reverse-tone mask method which is capable of eliminating metal overburden humps in a metal layer electroplated onto a substrate, is disclosed. Typically, the method includes providing a masking layer on a metal layer such as copper previously electroplated o... | 10/24/2006 |
| 7119435 | Semiconductor device with source/drain extension layer In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is f... | 10/10/2006 |
| 7067378 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/27/2006 |
| 7067391 | Method to form a metal silicide gate device A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the subst... | 06/27/2006 |
| 7060570 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/13/2006 |
| 7060569 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/13/2006 |
| 7056783 | Multiple operating voltage vertical replacement-gate (VRG) transistor An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped r... | 06/06/2006 |
| 7049230 | Method of forming a contact plug in a semiconductor device A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant sub... | 05/23/2006 |
| 7026232 | Systems and methods for low leakage strained-channel transistor The present invention facilitates semiconductor fabrication by providing methods of fabrication that mitigate leakage and apply strain to channel regions of transistor devices. A semiconductor device having gate structures, channel regions, and active regions is pro... | 04/11/2006 |
| 7012021 | Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the subs... | 03/14/2006 |
| 7005378 | Processes for fabricating conductive patterns using nanolithography as a patterning tool Nanolithographic deposition of metallic nanostructures using coated tips for use in microelectronics, catalysis, and diagnostics. AFM tips can be coated with metallic precursors and the precursors patterned on substrates. The patterned precursors can be converted to... | 02/28/2006 |
| 6979880 | Scalable high performance antifuse structure and process Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scal... | 12/27/2005 |
| 6974766 | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer de... | 12/13/2005 |
| 6969916 | Substrate having built-in semiconductor apparatus and manufacturing method thereof A substrate having a built-in semiconductor apparatus includes: a semiconductor apparatus which comprises a first semiconductor chip having a first electrode pad formed on a main surface thereof, a protruding portion which is in contact with the first semiconductor ... | 11/29/2005 |
