Bizarre Patents
An electrified table cloth for preventing crawling insects from gaining access to the consumer's food or drink.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7432184 | Integrated PVD system using designated PVD chambers A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one l... | 10/07/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7316974 | Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device A wiring pattern formation method in which a wiring pattern is formed by arranging, in a region which is demarcated by a partition wall, liquid material which includes an electrically conductive material, including: arranging a resin material around the periphery of... | 01/08/2008 |
| 7316972 | Contact hole formation method A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4, a process of depositing a dielectric film 5 on the BP... | 01/08/2008 |
| 7265044 | Method for forming bump on electrode pad with use of double-layered film A process for forming bumps on electrode pads for a wiring board including a substrate and a plurality of electrode pads. The process (a) forms a laminated two-layer film on the wiring board and forms a pattern of apertures at positions corresponding to the electrod... | 09/04/2007 |
| 7253409 | Electrochemical nano-patterning using ionic conductors The present invention provides nano-patterning based on flow of an ion current within an ionic conductor to bring ions in proximity to a microscope probe tip touching a surface of the conductor. These ions are then electrochemically reduced to form one or more featu... | 08/07/2007 |
| 7238586 | Seamless trench fill method utilizing sub-atmospheric pressure chemical vapor deposition technique A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2 | 07/03/2007 |
| 7232762 | Method for forming an improved low power SRAM contact A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (... | 06/19/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7172962 | Method of manufacturing a semiconductor device On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Ne... | 02/06/2007 |
| 7166533 | Phase change memory cell defined by a pattern shrink material process One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second electrode adjacent the phase-change material. The phase-change material has a... | 01/23/2007 |
| 7163854 | Fabrication method of a semiconductor device To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having a... | 01/16/2007 |
| 7125800 | Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the... | 10/24/2006 |
| 7067412 | Semiconductor device and method of manufacturing the same The present invention provides a semiconductor device including a plurality of wirings or conductive film patterns formed on a semiconductor substrate, and clearances are provided between the wirings or the conductive film patterns. On a corner or an end part of at ... | 06/27/2006 |
| 7052985 | Contact structure for an integrated semiconductor device A process forms an integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and ... | 05/30/2006 |
| 7049223 | Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a... | 05/23/2006 |
| 7033928 | Method of fabricating semiconductor device A method of fabricating a semiconductor device, including at least the steps of (a) forming a via-hole or trench throughout an electrically insulating layer, (b) forming a wiring material layer on the electrically insulating layer such that the via-hole or trench is... | 04/25/2006 |
| 7005378 | Processes for fabricating conductive patterns using nanolithography as a patterning tool Nanolithographic deposition of metallic nanostructures using coated tips for use in microelectronics, catalysis, and diagnostics. AFM tips can be coated with metallic precursors and the precursors patterned on substrates. The patterned precursors can be converted to... | 02/28/2006 |
| 6969301 | Filling plugs through chemical mechanical polish A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, ho... | 11/29/2005 |
| 6946392 | Filling plugs through chemical mechanical polish A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, ho... | 09/20/2005 |
| 6940171 | Multi-layer dielectric and method of forming same A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a... | 09/06/2005 |
| 6905956 | Multi-layer dielectric and method of forming same A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a... | 06/14/2005 |
| 6900121 | Laser thermal annealing to eliminate oxide voiding Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transis... | 05/31/2005 |
| 6888242 | Color contacts for a semiconductor package The surface of a solder ball and a conductive wire for a semiconductor package are coated with a predetermined colorant. Various colorants may be used according to the diameter and metal composition of the solder ball and the conductive wire. The colorant is formed ... | 05/03/2005 |
| 6812136 | Method of making a semiconductor device having a multilayer metal film of titanium/titanium nitride/tungsten/tungsten carbide According to the present invention, when a wiring layer using copper is formed, an interlayer insulation film is formed on a semiconductor substrate having a conductive portion of an element. A contact hole, which is connected to at least the conductive portion, is ... | 11/02/2004 |
| 6803308 | Method of forming a dual damascene pattern in a semiconductor device The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a semiconductor device by filling a via hole with a photoresist, using a re... | 10/12/2004 |
| 6787468 | Method of fabricating metal lines in a semiconductor device A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess regi... | 09/07/2004 |
| 6720253 | Method of manufacturing semiconductor device having an aluminum wiring layer A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on a interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner fil... | 04/13/2004 |
| 6696360 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in int... | 02/24/2004 |
| 6673718 | Methods for forming aluminum metal wirings An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surf... | 01/06/2004 |
| 6639285 | Method for fabricating a semiconductor device A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the layer of doped dielectric. A red... | 10/28/2003 |
| 6627549 | Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric l... | 09/30/2003 |
| 6627541 | Reflow method for construction of conductive vias A method of constructing a semiconductor device 10 is disclosed which includes a reflow step. The device 10 comprises a conductive via 20 electrically connected to a conductive interconnect 28. The formation of interconnect 28 can result in damage to cond... | 09/30/2003 |
| 6620534 | Film having enhanced reflow characteristics at low thermal budget A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In thi... | 09/16/2003 |
| 6599828 | Copper reflow process A manufacturable method for forming a highly reliable electrical interconnection. An electrical interconnection pattern is first formed in a dielectric layer on a semiconductor substrate as recessed regions in the dielectric layer. A conductive layer prim... | 07/29/2003 |
| 6594894 | Planar-processing compatible metallic micro-extrusion process Micromachined extrusions on the micrometer scale is realized using compressive stresses resulting from electromigration-induced mass transport in planarized conductors. Extrusions are formed through simple die patterns etched through a passivation layer o... | 07/22/2003 |
| 6566259 | Integrated deposition process for copper metallization Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plas... | 05/20/2003 |
| 6534396 | Patterned conductor layer pasivation method with dimensionally stabilized planarization Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is the... | 03/18/2003 |
| 6534398 | Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a... | 03/18/2003 |
| 6514876 | Pre-metal dielectric rapid thermal processing for sub-micron technology A process for forming silicate glass layers on substrates is disclosed. A silicate glass layer is first deposited onto a substrate, such as a semiconductor wafer. The wafer is then placed in a thermal processing chamber and heated in the presence of a rea... | 02/04/2003 |
