Class 438/643 - At least one layer forms a diffusion barrier

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes wherein at least one of the diverse conductive
No. of patents: 1147
Last issue date: 02/21/2012

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Number	Title	Issue Date
8119524	Method of manufacturing semiconductor device A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for cop...	02/21/2012
8043962	Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the da...	10/25/2011
8043963	Semiconductor device manufacturing method and semiconductor device manufacturing apparatus A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer (11) on a semiconductor substrate (2) including an ...	10/25/2011
8012872	Planarising damascene structures Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact ...	09/06/2011
7998859	Surface preparation process for damascene copper deposition A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the fol...	08/16/2011
7989342	Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallit...	08/02/2011
7960278	Method of film deposition The present invention is a method of film deposition that comprises a film-depositing step of supplying a high-melting-point organometallic material gas and a nitrogen-containing gas to a processing vessel that can be evacuated, so as to deposit a thin film of a met...	06/14/2011
7955971	Hybrid metallic wire and methods of fabricating same A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner ...	06/07/2011
7928006	Structure for a semiconductor device and a method of manufacturing the same There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) a...	04/19/2011
7906428	Modified via bottom structure for reliability enhancement The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures de...	03/15/2011
7867895	Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor platin...	01/11/2011
7867896	Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tan...	01/11/2011
7855143	Interconnect capping layer and method of fabrication The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an...	12/21/2010
7807568	Methods for reducing damage to substrate layers in deposition processes Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate to a process chamber comprising a dielectric layer having a feature formed therein. A barrier layer may be formed within ...	10/05/2010
7799676	Method of manufacturing a contact structure to avoid open issue A method of manufacturing a contact structure to avoid open issue is provided. The method includes the steps of providing a substrate with a contact region, forming an insulating layer to cover the substrate, forming a contact hole in the insulating layer to expose ...	09/21/2010
7781334	Method of manufacturing a semiconductor device with through-chip vias An electrode is formed in a hole extending partway into the substrate of a semiconductor device by depositing an insulating film and a barrier metal layer on the substrate surface and the interior of the hole, then filling the hole with a layer of electrode material...	08/24/2010
7781335	Method for fabricating semiconductor device A method for fabricating a semiconductor device includes the steps of: (a) forming a first insulating film having moisture absorbency on a substrate; (b) forming a dummy contact hole and a contact hole in the first insulating film; (c) heat-treating the substrate, t...	08/24/2010
7781333	Semiconductor device with gate structure and method for fabricating the semiconductor device A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-...	08/24/2010
7763538	Dual plasma treatment barrier film to reduce low-k damage A method is provided for creating a barrier layer (217) on a substrate comprising a dielectric layer (203) and a metal interconnect (211). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby for...	07/27/2010
7763539	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surfa...	07/27/2010
7741216	Metal line of semiconductor device and method for forming the same A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier...	06/22/2010
7713867	Method for forming a metal line in a semiconductor device A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second...	05/11/2010
7713866	Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, t...	05/11/2010
7709375	Semiconductor device including contact pattern and method for fabricating the same A method of fabricating a semiconductor device includes forming a barrier film over a semiconductor substrate and over a gate disposed on the substrate; forming a metal layer over the barrier film; selectively etching the metal layer and the barrier film to form a c...	05/04/2010
7704878	Contact spacer formation using atomic layer deposition A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal dep...	04/27/2010
7700479	Cleaning processes in the formation of integrated circuit interconnect structures A method for fabricating an integrated circuit includes providing a substrate, forming a low-k dielectric layer over the substrate, etching the low-k dielectric layer to form an opening in the low-k dielectric layer wherein an underlying metal is exposed through the...	04/20/2010
7666785	Method for fabricating semiconductor device with interface barrier A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten ...	02/23/2010
7632754	Method for forming metal line in a semiconductor device A method for forming a metal line of a semiconductor device includes forming an interlayer insulation film over a semiconductor substrate, forming a trench for exposing at least a portion of the semiconductor substrate by using a selective etching process, and formi...	12/15/2009
7601636	Implementation of a metal barrier in an integrated electronic circuit A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation s...	10/13/2009
7579272	Methods of forming low-k dielectric layers containing carbon nanostructures Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbo...	08/25/2009
7566654	Method for manufacturing a semiconductor device including interconnections having a smaller width A method for manufacturing a semiconductor device includes the steps of forming an interconnection layer including a top tungsten layer, forming a mask pattern on the tungsten layer, nitriding a portion of the tungsten layer in a plasma nitriding process to form a t...	07/28/2009
7544609	Method for integrating liner formation in back end of line processing A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insul...	06/09/2009
7514358	Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tan...	04/07/2009
7507659	Fabrication process of a semiconductor device A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface with a Cu—Mn alloy layer, depositing a first Cu layer over said Cu—Mn alloy layer without exposing sai...	03/24/2009
7491643	Method and structure for reducing contact resistance between silicide contact and overlying metallization A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal sil...	02/17/2009
7470617	Treating a liner layer to reduce surface oxides In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, wh...	12/30/2008
7442639	Method of forming plug of semiconductor device A method for forming a plug of a semiconductor device according to a preferred embodiment includes forming a metal wiring on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate having the metal wiring, forming a contact h...	10/28/2008
7438760	Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline...	10/21/2008
7435679	Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during...	10/14/2008
7429338	Surface modified colloidal abrasives, including stable bimetallic surface coated silica sols for chemical mechanical planarization A composition and an associated method for chemical mechanical planarization (or other polishing) are described. The composition includes a surface-modified abrasive modified with at least one stabilizer and at least one catalyst differing from the at least one stab...	09/30/2008

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Class 438/643 - At least one layer forms a diffusion barrier