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| Number | Title | Issue Date |
| 7981792 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, ... | 07/19/2011 |
| 7968455 | Copper deposition for filling features in manufacture of microelectronic devices A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal there... | 06/28/2011 |
| 7928005 | Method for forming narrow structures in a semiconductor device A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion... | 04/19/2011 |
| 7915161 | Post passivation interconnection schemes on top of IC chip A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 03/29/2011 |
| 7776739 | Semiconductor device interconnection contact and fabrication method A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion b... | 08/17/2010 |
| 7491642 | Electrical passivation of silicon-containing surfaces using organic layers Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passiv... | 02/17/2009 |
| 7482268 | Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used... | 01/27/2009 |
| 7432184 | Integrated PVD system using designated PVD chambers A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one l... | 10/07/2008 |
| 7381642 | Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used... | 06/03/2008 |
| 7371685 | Low stress barrier layer removal Apparatus and methods of fabricating an interconnect in a dielectric material, such as by a damascene or dual damascene processes. In specific, with the use of a barrier layer, such as to contain copper-containing materials used in the fabrication of the interconnec... | 05/13/2008 |
| 7368330 | Semiconductor device having fuse circuit on cell region and method of fabricating the same A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is p... | 05/06/2008 |
| 7368379 | Multi-layer interconnect structure for semiconductor devices An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers ... | 05/06/2008 |
| 7361586 | Preamorphization to minimize void formation Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, f... | 04/22/2008 |
| 7361590 | Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device includes: preparing a semiconductor element having a first metal layer made of first metal on a surface thereof, and a metal substrate made of second metal, the metal substrate having a fourth metal layer made of four... | 04/22/2008 |
| 7341942 | Method for forming metal line of semiconductor device A method for forming a metal line of a semiconductor device forms an aluminum line having an excellent orientation. A specific resistance of a metal line is reduced, thereby enabling sufficient supply of a desired electric current. The method includes steps of formi... | 03/11/2008 |
| 7335584 | Method of using SACVD deposition and corresponding deposition reactor A method is provided for using SACVD deposition to deposit at least one layer of dielectric material inside a deposition reactor during the fabrication of at least one semiconductor integrated circuit. According to the method, a reaction chamber is provided for carr... | 02/26/2008 |
| 7319270 | Multi-layer electrode and method of forming the same An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, form... | 01/15/2008 |
| 7312150 | Method of forming cobalt disilicide layer and method of manufacturing semiconductor device using the same A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device us... | 12/25/2007 |
| 7301238 | Structure and method of forming an enlarged head on a plug to eliminate the enclosure requirement The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the to... | 11/27/2007 |
| 7300872 | Method for manufacturing semiconductor device using dual-damascene pattern A method for manufacturing a semiconductor device using a dual-damascene pattern, where a photosensitive film is coated instead of a dielectric material, the photosensitive film is cured, and the photosensitive film is entirely etched. The method includes forming a ... | 11/27/2007 |
| 7294565 | Method of fabricating a wire bond pad with Ni/Au metallization A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN... | 11/13/2007 |
| 7294578 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 11/13/2007 |
| 7288484 | Photoresist strip method for low-k dielectrics The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer... | 10/30/2007 |
| 7279417 | Use of metallocenes to inhibit copper oxidation during semiconductor processing Methods for protecting an exposed copper surface of a partially fabricated IC from oxidation during exposure to an oxygen-containing environment are disclosed. The methods involve treating the exposed copper surface with a metallocene compound in order to minimize f... | 10/09/2007 |
| 7276451 | Method for manufacturing semiconductor device Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a bit line contact region and a storage node contact region are simultaneously formed, and then a storage node contact hole is formed after a form of bit line ... | 10/02/2007 |
| 7262125 | Method of forming low-resistivity tungsten interconnects Methods and apparatus for preparing a low-resistivity tungsten film on a substrate are provided. Methods involve the formation of a tungsten nucleation layer on a substrate using pulsed nucleation layer (PNL) techniques and depositing a bulk tungsten layer thereon. ... | 08/28/2007 |
| 7259025 | Ferromagnetic liner for conductive lines of magnetic memory cells A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to swi... | 08/21/2007 |
| 7253092 | Tungsten plug corrosion prevention method using water Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs.... | 08/07/2007 |
| 7253113 | Methods for using a silylation technique to reduce cell pitch in semiconductor devices A method for forming a semiconductor device having a reduced pitch is provided. The method includes providing a substrate, forming a material layer over the substrate, forming a photoresist layer over the material layer, exposing a top surface of the photoresist lay... | 08/07/2007 |
| 7232757 | Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the su... | 06/19/2007 |
| 7233069 | Interconnection substrate and fabrication method thereof An interconnection substrate includes: an interconnection layer region where at least a first conductor layer and a second conductor layer are vertically stacked in that order on a substrate, with the first conductor layer and second conductor layer containing condu... | 06/19/2007 |
| 7217647 | Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer ... | 05/15/2007 |
| 7217655 | Electroplated CoWP composite structures as copper barrier layers A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a m... | 05/15/2007 |
| 7214621 | Methods of forming devices associated with semiconductor constructions The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates. ... | 05/08/2007 |
| 7214602 | Method of forming a conductive structure A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further inclu... | 05/08/2007 |
| 7205588 | Metal fuse for semiconductor devices A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2 exposing at least a por... | 04/17/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7189638 | Method for manufacturing metal structure using trench A method for manufacturing a metal structure using a trench includes etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the trench, stacking an insulating layer over the seed layer, removing a po... | 03/13/2007 |
| 7186643 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated cir... | 03/06/2007 |
| 7176127 | Method of manufacturing semiconductor device having through hole with adhesion layer thereon An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for form... | 02/13/2007 |
