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| Number | Title | Issue Date |
| 7629252 | Conformal electroless deposition of barrier layer materials Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises provid... | 12/08/2009 |
| 7517794 | Method for fabricating nanoscale features One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon ... | 04/14/2009 |
| 7368379 | Multi-layer interconnect structure for semiconductor devices An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers ... | 05/06/2008 |
| 7361595 | Transition metal thin film forming method A semiconductor substrate is placed in a predetermined processing vessel, and oxygen gas activated by, e.g. conversion into a plasma is supplied onto an insulating film. The surfaces of an interlevel insulating film and insulating film are exposed to the activated o... | 04/22/2008 |
| 7344977 | Method of electroplating a substance over a semiconductor substrate The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a si... | 03/18/2008 |
| 7344973 | Semiconductor device and method of manufacturing the same Provided are a semiconductor device, adapted to be capable of fabricating the device having improved resistance characteristic by decreasing dishing of solid phase epitaxy (SPE) silicon during planarization in a landing plug forming process via use of SPE silicon, a... | 03/18/2008 |
| 7338893 | Integration of pore sealing liner into dual-damascene methods and devices A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conduct... | 03/04/2008 |
| 7329607 | Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transforme... | 02/12/2008 |
| 7329956 | Dual damascene cleaning method A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the openi... | 02/12/2008 |
| 7288474 | Suspension for filling via holes in silicon and method for making the same A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes... | 10/30/2007 |
| 7276442 | Method for forming a metallization layer A method for depositing metal on a semiconductor device having a substrate, an exposed first surface, and an exposed second surface is provided. Metal ions are deposited on the exposed first surface and on the exposed second layer by applying a first voltage between... | 10/02/2007 |
| 7271095 | Process for producing metallic interconnects and contact surfaces on electronic components A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from pos... | 09/18/2007 |
| 7262500 | Interconnection structure In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a diff... | 08/28/2007 |
| 7259025 | Ferromagnetic liner for conductive lines of magnetic memory cells A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to swi... | 08/21/2007 |
| 7247560 | Selective deposition of double damascene metal A method has been disclosed that allows the selective deposition of the metal for double damascene silicon wafer processing. This selective deposition allows the metal to be deposited only in the via holes, contact holes, channels or where ever the deposition is tar... | 07/24/2007 |
| 7241696 | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The... | 07/10/2007 |
| 7238610 | Method and apparatus for selective deposition A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then coated with an inhibiting material. Finally, a source material is select... | 07/03/2007 |
| 7214979 | Selectively deposited silicon oxide layers on a silicon substrate A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of... | 05/08/2007 |
| 7208421 | Method and apparatus for production of metal film or the like In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a diff... | 04/24/2007 |
| 7202154 | Suspension for filling via holes in silicon and method for making the same A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes... | 04/10/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7192893 | Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relat... | 03/20/2007 |
| 7179361 | Method of forming a mass over a semiconductor substrate The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a si... | 02/20/2007 |
| 7172966 | Method for fabricating metallic interconnects on electronic components The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnec... | 02/06/2007 |
| 7163888 | Direct imprinting of etch barriers using step and flash imprint lithography A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16 | 01/16/2007 |
| 7138304 | Method for forming thin film pattern, device and production method therefor, electro-optical apparatus and electronic apparatus, and production method for active matrix substrate A method for forming a thin film pattern includes the step of ejecting a plurality of liquid droplets of a function liquid at predetermined pitches between banks, wherein each of the predetermined pitches is larger than a diameter of the liquid droplet and the prede... | 11/21/2006 |
| 7135403 | Method for forming metal interconnection line in semiconductor device Disclosed is a method for forming a metal interconnection line in a semiconductor device. The method includes the steps of: forming an inter-layer insulation layer on a substrate, the inter-layer insulation layer having at least one contact hole exposing a portion o... | 11/14/2006 |
| 7129164 | Method for forming a multi-layer low-K dual damascene A damascene structure and method for forming the same in a multi-density dielectric insulating layer the method including providing a substrate; forming at least a first layer comprising silicon oxide according to a first process having a first density; forming at l... | 10/31/2006 |
| 7126232 | Defect repair apparatus for an electronic device A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD of other electronic device has defects. Described is a method of transferring a single or multi-l... | 10/24/2006 |
| 7105434 | Advanced seed layery for metallic interconnects One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one open... | 09/12/2006 |
| 7087997 | Copper to aluminum interlayer interconnect using stud and via liner Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten... | 08/08/2006 |
| 7087510 | Method of making bondable leads using positive photoresist and structures made therefrom A microelectronic component having a plurality of leads are formed at their tip end with bondable material using a process including a mask of positive photoresist material. The leads can be rendered peelable from the substrate by, for example, plasma undercutting t... | 08/08/2006 |
| 7064068 | Method to improve planarity of electroplated copper Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used du... | 06/20/2006 |
| 7049231 | Methods of forming capacitors In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A ... | 05/23/2006 |
| 6967154 | Enhanced atomic layer deposition A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substr... | 11/22/2005 |
| 6964922 | Methods for forming metal interconnections for semiconductor devices having multiple metal depositions Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the cond... | 11/15/2005 |
| 6951804 | Formation of a tantalum-nitride layer A method of forming a tantalum-nitride layer (204) for integrated circuit fabrication is disclosed. Alternating or co-reacting pulses of a tantalum containing precursor and a nitrogen containing precursor are provided to a chamber (100) to form layers ... | 10/04/2005 |
| 6943411 | Semiconductor device including a low resistance wiring layer A semiconductor device can include a low resistance wiring layer (13) formed in, and extending along a base material. A number of element regions (14) are formed separate from one another, each in contact with wiring layer (13). A circuit elemen... | 09/13/2005 |
| 6924226 | Methods for making multiple seed layers for metallic interconnects One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one open... | 08/02/2005 |
| 6921717 | Method for forming metal lines Disclosed is a method for forming metal lines, which comprises the following steps of: preparing a semiconductor substrate having a lower metal line; successively forming a polymer dielectric film and an oxide film on the substrate, the polymer dielectric film and t... | 07/26/2005 |
