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| Number | Title | Issue Date |
| 7670948 | Semiconductor device having diffusion barriers and a method of preventing diffusion of copper in a metal interconnection of a semiconductor device Embodiments of a semiconductor device and a method of fabricating the same may include an insulating layer formed on a substrate and having a predetermined hole, a metal interconnection formed in the hole and protruding relative to the insulating layer, a first barr... | 03/02/2010 |
| 7651942 | Metal interconnect structure and method A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying... | 01/26/2010 |
| 7585766 | Methods of manufacturing copper interconnect systems An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 09/08/2009 |
| 7576001 | Manufacturing method for semiconductor device A semiconductor device manufacturing method for suppressing surface roughness of a Low-k insulating film during etching. In a laminated structure comprising a layer having formed thereon a lower copper wiring, a SiC film and a SiOC film, a via and an upper copper wi... | 08/18/2009 |
| 7572729 | Method of manufacturing semiconductor device A method of manufacturing semiconductor devices, including the steps of forming an insulating layer on a semiconductor substrate in which predetermined structures are formed, and etching the insulating layer to expose a predetermined region of the semiconductor subs... | 08/11/2009 |
| 7550379 | Alignment mark, use of a hard mask material, and method In a method to produce an alignment mark, an oxide layer and sacrificial layer are processed to comprise recesses. The recesses are filled with a filler material. During filling the recesses, a layer of filler material is formed on the sacrificial layer. The layer o... | 06/23/2009 |
| 7531450 | Method of fabricating semiconductor device having contact hole with high aspect-ratio Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper... | 05/12/2009 |
| 7494922 | Small electrode for phase change memories A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exp... | 02/24/2009 |
| 7491641 | Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first... | 02/17/2009 |
| 7476614 | Method of fabricating semiconductor device A method of fabricating a semiconductor device comprises sequentially forming a first conductive layer, a first insulating interlayer, a second conductive layer, and a second insulating interlayer on a semiconductor substrate. A mask layer is formed on the second in... | 01/13/2009 |
| 7439144 | CMOS gate structures fabricated by selective oxidation A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with convention... | 10/21/2008 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7435673 | Methods of forming integrated circuit devices having metal interconnect structures therein Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insul... | 10/14/2008 |
| 7435676 | Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is... | 10/14/2008 |
| 7410892 | Methods of fabricating integrated circuit devices having self-aligned contact structures An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first in... | 08/12/2008 |
| 7402514 | Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the step... | 07/22/2008 |
| 7402515 | Method of forming through-silicon vias with stress buffer collars and resulting devices A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. ... | 07/22/2008 |
| 7396762 | Interconnect structures with linear repair layers and methods for forming such interconnection structures Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a condu... | 07/08/2008 |
| 7393779 | Shrinking contact apertures through LPD oxide Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to t... | 07/01/2008 |
| 7389581 | Method of forming compliant contact structures A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the sub... | 06/24/2008 |
| 7387961 | Dual damascene with via liner A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in t... | 06/17/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7378339 | Barrier for use in 3-D integration of circuits A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circ... | 05/27/2008 |
| 7371677 | Laterally grown nanotubes and method of formation A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portio... | 05/13/2008 |
| 7372101 | Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the t... | 05/13/2008 |
| 7363694 | Method of testing using compliant contact structures, contactor cards and test system A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the sub... | 04/29/2008 |
| 7365408 | Structure for photolithographic applications using a multi-layer anti-reflection coating A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring feat... | 04/29/2008 |
| 7365001 | Interconnect structures and methods of making thereof A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in ... | 04/29/2008 |
| 7361589 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/22/2008 |
| 7361605 | System and method for removal of photoresist and residues following contact etch with a stop layer present In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one con... | 04/22/2008 |
| 7358568 | Low resistance semiconductor process and structures A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitri... | 04/15/2008 |
| 7358597 | UV-activated dielectric layer A dielectric layer on a semiconductor substrate is made porous by radiation with UV light. The dielectric material contains a photosensitive moiety that absorbs UV radiation and dissociates from the dielectric material. The UV-activated material then may be diffused... | 04/15/2008 |
| 7358170 | Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 04/15/2008 |
| 7352064 | Multiple layer resist scheme implementing etch recipe particular to each layer Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first plan... | 04/01/2008 |
| 7344974 | Metallization method of semiconductor device A method for forming a metallization contact in a semiconductor device includes the steps of: (a) forming an insulating layer on a semiconductor substrate including an active device region; (b) forming a contact hole to expose a portion of the active device region b... | 03/18/2008 |
| 7344976 | Method for fabricating nonvolatile semiconductor memory device An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conducti... | 03/18/2008 |
| 7342301 | Connection device with actuating element for changing a conductive state of a via A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of t... | 03/11/2008 |
| 7341936 | Semiconductor device and method of manufacturing the same A semiconductor device manufacturing method comprises the steps of forming a metal film (24) on an organic interlayer insulating film (22) formed over a semiconductor substrate to get a metal diffusion preventing metal carbide film (23) on a bou... | 03/11/2008 |
| 7338871 | Method for fabricating semiconductor device The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conduc... | 03/04/2008 |
| 7338895 | Method for dual damascene integration of ultra low dielectric constant porous materials A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k ... | 03/04/2008 |