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| Number | Title | Issue Date |
| 8187969 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substr... | 05/29/2012 |
| 8183151 | Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive ... | 05/22/2012 |
| 8183152 | Method of fabricating semiconductor device A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are forme... | 05/22/2012 |
| 8153519 | Method for fabricating semiconductor device using spacer patterning A method for fabricating a semiconductor device includes depositing and stacking a hard mask layer and a sacrificial layer over an etch target layer forming a mask pattern with holes defined therein over the sacrificial layer, forming first pillars filling the holes... | 04/10/2012 |
| 8148260 | Semiconductor memory device and method of forming the same Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure in... | 04/03/2012 |
| 8148259 | Method for manufacturing semiconductor device The present invention offers a method for forming an opening portion by a simple process without using a photomask or a resist. Further, the present invention proposes a method for manufacturing a semiconductor device at low cost. A plurality of light absorbing laye... | 04/03/2012 |
| 8133809 | Method to fabricate thin metal via interconnects on copper wires in MRAM devices A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and photoresist layer are successively formed on a substrate having a copp... | 03/13/2012 |
| 8129269 | Method of improving mechanical properties of semiconductor interconnects with nanoparticles In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the propertie... | 03/06/2012 |
| 8124527 | CMP process flow for MEMS The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication... | 02/28/2012 |
| 8119523 | Method for fabricating semiconductor device using dual damascene process A method for fabricating a semiconductor device using a dual damascene process is provided. The method includes forming a dielectric layer over a conductive layer, forming a via hole exposing the conducting layer by selectively etching the dielectric layer, projecti... | 02/21/2012 |
| 8114769 | Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) scheme A method for semiconductor fabrication using a trench first metal hard mask (TFMHM) process for damascene structures includes forming a secondary metal hard mask layer above a first metal hard mask layer after trench opening for the via (and trench) etching. The sec... | 02/14/2012 |
| 8105940 | Power distribution in a vertically integrated circuit A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the pat... | 01/31/2012 |
| 8105938 | Semiconductor substrate and method of manufacturing the same There is provided a method of manufacturing a semiconductor substrate. The method includes: (a) forming a wiring pattern on a substrate; (b) covering the wiring pattern with an insulating resin, thereby forming a first insulating layer; (c) forming a second insulati... | 01/31/2012 |
| 8105939 | LDMOS transistor and method for manufacturing the same A LDMOS transistor and a method for manufacturing the same are disclosed. A lateral double diffused metal oxide semiconductor (LDMOS) transistor includes a first dielectric layer formed on a top surface of a substrate; a plurality of second dielectric layers on a to... | 01/31/2012 |
| 8084357 | Method for manufacturing a dual damascene opening comprising a trench opening and a via opening A method for manufacturing a multi cap layer includes providing a substrate, forming a multi cap layer comprising a first cap layer and a second cap layer formed thereon on the substrate, forming a patterned metal hard mask layer on the multi cap layer, and performi... | 12/27/2011 |
| 8076236 | SRAM bit cell with self-aligned bidirectional local interconnects Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodime... | 12/13/2011 |
| 8071474 | Method of manufacturing semiconductor device suitable for forming wiring using damascene method (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Condu... | 12/06/2011 |
| 8058166 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing... | 11/15/2011 |
| 8053358 | Methods of forming integrated circuit devices using contact hole spacers to improve contact isolation Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulatin... | 11/08/2011 |
| 8043961 | Method of forming a bond pad A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabricati... | 10/25/2011 |
| 8043960 | Contact structure of semiconductor devices and method of fabricating the same A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the conca... | 10/25/2011 |
| 8034711 | Bonding structure and fabrication thereof A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protectio... | 10/11/2011 |
| 8034712 | Method of fabricating dual damascene structure A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are pattern... | 10/11/2011 |
| 8030207 | Method of manufacturing a semiconductor device and semiconductor device A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom ... | 10/04/2011 |
| 8030208 | Bonding method for through-silicon-via based 3D wafer stacking There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a solderin... | 10/04/2011 |
| 8026170 | Method of forming a single-layer metal conductors with multiple thicknesses A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are a... | 09/27/2011 |
| 8026169 | Cu annealing for improved data retention in flash memory devices Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmospher... | 09/27/2011 |
| 8026172 | Method of forming contact hole arrays using a hybrid spacer technique One embodiment of the invention provides a method of forming a plurality of contact holes, including forming a first feature and a second feature over an underlying material, forming sidewall spacers on the first and second features, removing the first and second fe... | 09/27/2011 |
| 8026171 | Method of fabricating metal interconnection and method of fabricating image sensor using the same A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formati... | 09/27/2011 |
| 8021978 | Methods of fabricating flash memory devices having shared sub active regions Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact pl... | 09/20/2011 |
| 8021977 | Methods of forming contact structures and semiconductor devices fabricated using contact structures Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sid... | 09/20/2011 |
| 8021979 | Method of manufacturing semiconductor device To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chambe... | 09/20/2011 |
| 8017518 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device includes the steps of: (a) forming a low dielectric constant film over a semiconductor substrate; (b) forming a recess in the low dielectric constant film; (c) after the step (b), sequentially performing the steps of... | 09/13/2011 |
| 8008190 | Method of manufacturing semiconductor device Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant fr... | 08/30/2011 |
| 8008192 | Conductive interconnect structures and formation methods using supercritical fluids Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the... | 08/30/2011 |
| 8008188 | Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portion... | 08/30/2011 |
| 8008189 | Semiconductor device manufacturing method, semiconductor device, and semiconductor wafer structure A semiconductor device manufacturing method, includes the steps of forming an insulating film over a semiconductor substrate, thinning selectively a thick portion, whose film thickness is thicker than a reference value, of the insulating film, forming contact holes ... | 08/30/2011 |
| 8008191 | Semiconductor device and method for manufacturing the same A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semic... | 08/30/2011 |
| 8003522 | Method for forming trenches with wide upper portion and narrow lower portion A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface ar... | 08/23/2011 |
| 8003523 | Methods for forming a plurality of contact holes in a microelectric device A method including: forming a dielectric layer over a substrate of a microelectronic device; forming a photoresist layer over the dielectric layer; performing a first exposure of the photoresist layer to permit portions of the dielectric layer to be removed at a fir... | 08/23/2011 |
