Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 8008187 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etch... | 08/30/2011 |
| 7977237 | Fabricating vias of different size of a semiconductor device by splitting the via patterning process When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent s... | 07/12/2011 |
| 7884011 | Semiconductor device and method of manufacture thereof A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of wh... | 02/08/2011 |
| 7855142 | Methods of forming dual-damascene metal interconnect structures using multi-layer hard masks Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked com... | 12/21/2010 |
| 7851354 | Semiconductor memory device having local etch stopper and method of manufacturing the same A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode... | 12/14/2010 |
| 7790607 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etch... | 09/07/2010 |
| 7732326 | Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric laye... | 06/08/2010 |
| 7727885 | Reduction of punch-thru defects in damascene processing A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop lay... | 06/01/2010 |
| 7691738 | Metal line in semiconductor device and fabricating method thereof A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer... | 04/06/2010 |
| 7678690 | Semiconductor device comprising a contact structure with increased etch selectivity By providing additional etch stop layers and/or etch protection layers, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. Consequently, conductive line ... | 03/16/2010 |
| 7553758 | Method of fabricating interconnections of microelectronic device using dual damascene process Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower inter... | 06/30/2009 |
| 7553759 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier. Inter-metal dielectric (IMD) layers (e.g. having via holes formed over an et... | 06/30/2009 |
| 7524757 | Method for manufacturing multi-level transistor comprising forming selective epitaxial growth layer A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dum... | 04/28/2009 |
| 7521357 | Methods of forming metal wiring in semiconductor devices using etch stop layers A method of forming a metal wiring in a semiconductor device can include forming an etch stop layer outside a contact hole formed in an insulation layer and avoiding forming the etch stop layer inside the contact hole. A conductive layer can be formed on the etch st... | 04/21/2009 |
| 7435682 | Method of manufacturing semiconductor device Disclosed is a method of manufacturing a semiconductor device comprising forming an insulating film above a substrate, forming a recess in the insulating film, successively forming an underlying layer, an immediate layer and a resist film above the insulating film h... | 10/14/2008 |
| 7372156 | Method to fabricate aligned dual damascene openings An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patt... | 05/13/2008 |
| 7372157 | Semiconductor device including titanium wires and manufacturing method therefor A first insulating film consisting of an insulating material is formed on a major surface of a semiconductor substrate. On the first insulating film, a wire comprising a first conductive layer, which contains one of elemental Ti and a Ti compound, is formed. Cover f... | 05/13/2008 |
| 7364924 | Silicon phosphor electroluminescence device with nanotip electrode An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top elect... | 04/29/2008 |
| 7361605 | System and method for removal of photoresist and residues following contact etch with a stop layer present In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one con... | 04/22/2008 |
| 7361587 | Semiconductor contact and nitride spacer formation system and method The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate conn... | 04/22/2008 |
| 7354855 | Semiconductor device and a method of manufacturing the same For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed the... | 04/08/2008 |
| 7351635 | Method of fabricating microelectronic device using super critical fluid Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step. In one illustrative embodiment, the method includes preparing a substr... | 04/01/2008 |
| 7341937 | Semiconductor device and method of manufacturing same Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on ... | 03/11/2008 |
| 7338899 | Method of forming contact plug in semiconductor device A method of forming a contact plug of a semiconductor device wherein, after a contact plug is formed in an interlayer insulation film, the interlayer insulation film is selectively etched so that the top surface of the contact plug is higher than the top surface of ... | 03/04/2008 |
| 7335584 | Method of using SACVD deposition and corresponding deposition reactor A method is provided for using SACVD deposition to deposit at least one layer of dielectric material inside a deposition reactor during the fabrication of at least one semiconductor integrated circuit. According to the method, a reaction chamber is provided for carr... | 02/26/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7335598 | Chemical-mechanical polishing method A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a ch... | 02/26/2008 |
| 7329912 | Device and methods for CMOS image sensor having borderless contact A photodiode device including a well located in a substrate, a floating node located in the well and shallow trench isolation (STI) regions located over and laterally opposing the floating node. A borderless contact buffer layer is located over at least the floating... | 02/12/2008 |
| 7326645 | Methods for forming copper interconnect of semiconductor devices Methods for forming a copper interconnect of a semiconductor device are disclosed. A disclosed method comprises forming a lower metal interconnect; sequentially depositing a capping layer, a first insulating layer, and a second insulating layer on the lower metal in... | 02/05/2008 |
| 7323408 | Metal barrier cap fabrication by polymer lift-off A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etc... | 01/29/2008 |
| 7321155 | Offset spacer formation for strained channel CMOS transistor A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and... | 01/22/2008 |
| 7315082 | Semiconductor device having integrated circuit contact A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch ... | 01/01/2008 |
| 7314651 | Film forming method and film forming device A plasma 10 is generated within a film formation chamber 2, and mainly a nitrogen gas 11 is excited within the film formation chamber 2. Then, the excited nitrogen gas 11 is mixed with a diborane gas 13 diluted with a hydrog... | 01/01/2008 |
| 7312146 | Semiconductor device interconnect fabricating techniques The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwic... | 12/25/2007 |
| 7300840 | MIM capacitor structure and fabricating method thereof A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor op... | 11/27/2007 |
| 7291553 | Method for forming dual damascene with improved etch profiles A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the ... | 11/06/2007 |
| 7288432 | Electronic devices with small functional elements supported on a carrier Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relat... | 10/30/2007 |
| 7288476 | Controlled dry etch of a film The controlled etch into a substrate or thick homogeneous film is accomplished by introducing a sacrificial film to gauge the depth to which the substrate/thick film has been etched. Optical endpointing the etch of the sacrificial film on the etch stop layer allows ... | 10/30/2007 |
| 7282447 | Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect... | 10/16/2007 |
| 7279118 | Compositions of matter and barrier layer compositions In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between ... | 10/09/2007 |
