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| Number | Title | Issue Date |
| 7888261 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated cir... | 02/15/2011 |
| 7510961 | Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a diel... | 03/31/2009 |
| 7413979 | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an int... | 08/19/2008 |
| 7371509 | Resist pattern and reflow technology A reflow stabilizing solution for treating photoresist patterns and a reflow technology are disclosed. The reflow stabilizing solution comprises a polymer and is applied after the photoresist material has been developed and patterned. By treating the photoresist wit... | 05/13/2008 |
| 7351656 | Semiconductor device having oxidized metal film and manufacture method of the same A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in ... | 04/01/2008 |
| 7348618 | Flash memory cell having reduced floating gate to floating gate coupling According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate sta... | 03/25/2008 |
| 7335596 | Method for fabricating copper-based interconnections for semiconductor device Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, an... | 02/26/2008 |
| 7335570 | Method of forming insulating films, capacitances, and semiconductor devices Insulating metal oxide or nitride films are deposited by RF magnetron sputtering. During sputtering, the atmospheric gas comprises an oxygen or nitride compound gas and an inert gas. The proportion of the inert gas is decreased to 25 atom % or lower. By this sputter... | 02/26/2008 |
| 7316974 | Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device A wiring pattern formation method in which a wiring pattern is formed by arranging, in a region which is demarcated by a partition wall, liquid material which includes an electrically conductive material, including: arranging a resin material around the periphery of... | 01/08/2008 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7288472 | Method and system for performing die attach using a flame Embodiments of a method for attaching a die to a substrate using a flame or other heat source are disclosed. The flame may be produced by combustible gas. Also disclosed are embodiments of a system for performing die attach using a flame. Other embodiments are descr... | 10/30/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7282433 | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads,... | 10/16/2007 |
| 7265044 | Method for forming bump on electrode pad with use of double-layered film A process for forming bumps on electrode pads for a wiring board including a substrate and a plurality of electrode pads. The process (a) forms a laminated two-layer film on the wiring board and forms a pattern of apertures at positions corresponding to the electrod... | 09/04/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7253521 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper in combination with diffusion barriers, rather than aluminum, to form the wi... | 08/07/2007 |
| 7220665 | H plasma treatment Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive l... | 05/22/2007 |
| 7217632 | Isolation methods in semiconductor devices Methods of forming a device isolation layer in a semiconductor substrate are disclosed. A disclosed method includes: forming a trench in a field area of a semiconductor substrate, growing a SiON layer on an inside of the trench by annealing in an ambience of NO gas,... | 05/15/2007 |
| 7218651 | Arrangement for the generation of a pulsed laser beam of high average output The invention is directed to an arrangement for generating a pulsed laser beam with high average output, in particular for generating a hot plasma which emits extreme ultraviolet (EUV) radiation. It is the object of the invention to find a novel possibility for gene... | 05/15/2007 |
| 7205230 | Process for manufacturing a wiring board having a via A process for manufacturing a wiring board comprising a substrate made of an insulation material and having first and second surfaces, first and second conductor patterns formed on the first and second surfaces, respectively, and a via conductor penetrating the subs... | 04/17/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7188411 | Process for forming portions of a compound material inside a cavity A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial m... | 03/13/2007 |
| 7186643 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated cir... | 03/06/2007 |
| 7172962 | Method of manufacturing a semiconductor device On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Ne... | 02/06/2007 |
| 7169706 | Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The ... | 01/30/2007 |
| 7164191 | Low relative permittivity SiOfilm including a porous material for use with a semiconductor device A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivit... | 01/16/2007 |
| 7160808 | Chuck for supporting wafers with a fluid A method of relieving surface stress on a thin wafer by removing a small portion of the wafer substrate, the substrate being removed by applying a warm solution of KOH to the backside of the wafer while the wafer spins. The wafer may be supported on a rotatable plat... | 01/09/2007 |
| 7144808 | Integration flow to prevent delamination from copper The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer... | 12/05/2006 |
| 7141880 | Metal line stacking structure in semiconductor device and formation method thereof The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substr... | 11/28/2006 |
| 7132362 | Semiconductor device with contacts having uniform contact resistance and method for manufacturing the same A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etch... | 11/07/2006 |
| 7125800 | Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the... | 10/24/2006 |
| 7121286 | Method for cleaning a manufacturing apparatus and a manufacturing apparatus A method for cleaning a manufacturing apparatus, includes introducing a cleaning gas including fluorine so as to flow from upstream toward an outlet port in a reaction chamber; and flowing a protective gas which reacts with the fluorine from a vicinity of the outlet... | 10/17/2006 |
| 7115503 | Method and apparatus for processing thin metal layers A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern... | 10/03/2006 |
| 7105382 | Self-aligned electrodes contained within the trenches of an electroosmotic pump A device where the electrodes of an electroosmotic pump are located directly in the flow-producing region of the electroosmotic pump is described as well as methods of forming such a device. Placing the electrodes of an electroosmotic pump directly in the flow-produ... | 09/12/2006 |
| 7105914 | Integrated circuit and seed layers Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the i... | 09/12/2006 |
| 7091124 | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an int... | 08/15/2006 |
| 7091611 | Multilevel copper interconnects with low-k dielectrics and air gaps Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which ... | 08/15/2006 |
| 7074714 | Method of depositing a metal seed layer on semiconductor substrates We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a d... | 07/11/2006 |
| 7067421 | Multilevel copper interconnect with double passivation Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance and include methods for forming multilevel wiring interconnects in an integrated circuit... | 06/27/2006 |
