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| Number | Title | Issue Date |
| 8114768 | Electromigration resistant via-to-line interconnect A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal ... | 02/14/2012 |
| 8110495 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between up... | 02/07/2012 |
| 8105937 | Conformal adhesion promoter liner for metal interconnects A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copp... | 01/31/2012 |
| 8101517 | Semiconductor device and method for making same One or more embodiments may relate to a method for making a semiconductor structure, the method including: forming an opening at least partially through a workpiece; and forming an enclosed cavity within the opening, the forming the cavity comprising forming a paste... | 01/24/2012 |
| 8062970 | Production method for semiconductor device The present invention is a production method for a semiconductor device equipped with a conductive film with predetermined film thickness on a sidewall of a concave portion formed in an insulating film, and comprises a step of forming the concave portion in the insu... | 11/22/2011 |
| 8058165 | Semiconductor device and method of manufacturing the same A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal lay... | 11/15/2011 |
| 8026168 | Semiconductor device containing an aluminum tantalum carbonitride barrier film and method of forming The method includes providing a substrate containing a dielectric layer having a recessed feature and forming a aluminum tantalum carbonitride barrier film over a surface of the recessed feature. The aluminum tantalum carbonitride barrier film is formed by depositin... | 09/27/2011 |
| 8003519 | Systems and methods for back end of line processing of semiconductor circuits A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by forma... | 08/23/2011 |
| 7998857 | Integrated circuit and process for fabricating thereof A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first co... | 08/16/2011 |
| 7994049 | Manufacturing method of semiconductor device including filling a connecting hole with metal film The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal ... | 08/09/2011 |
| 7994048 | Method of manufacturing a through electrode A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon sub... | 08/09/2011 |
| 7977235 | Method for manufacturing a semiconductor device with metal-containing cap layers A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, forming a patterned mask ... | 07/12/2011 |
| 7960276 | Conductor-dielectric structure and method for fabricating A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed lay... | 06/14/2011 |
| 7955969 | Ultra thin FET Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a ri... | 06/07/2011 |
| 7935626 | Semiconductor device and method for manufacturing the same In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conduct... | 05/03/2011 |
| 7935625 | Method of forming a metal line of a semiconductor memory device A method of forming a metal line of a semiconductor memory device is disclosed. An interlayer insulating layer, an etch-stop layer, a trench oxide layer, a hard mask layer and a photoresist layer are laminated over a semiconductor substrate in which a contact is for... | 05/03/2011 |
| 7867891 | Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed. ... | 01/11/2011 |
| 7863183 | Method for fabricating last level copper-to-C4 connection with interfacial cap structure The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing Co... | 01/04/2011 |
| 7829456 | Method to modulate coverage of barrier and seed layer using titanium nitride Methods for processing substrates are provided herein. In some embodiments, a method for processing substrates includes providing to a process chamber a substrate comprising an exposed dielectric layer having a feature formed therein. A mask layer comprising titaniu... | 11/09/2010 |
| 7820545 | Methods of forming conductive interconnects The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 10/26/2010 |
| 7759246 | Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor ... | 07/20/2010 |
| 7678689 | Method of fabricating memory device Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed t... | 03/16/2010 |
| 7678688 | Method for forming metal interconnection in image sensor A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming... | 03/16/2010 |
| 7632751 | Semiconductor device having via connecting between interconnects A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed... | 12/15/2009 |
| 7618888 | Temperature-controlled metallic dry-fill process A method for performing ionized physical vapor deposition (iPVD) is described, whereby the substrate temperature can be rapidly changed to control a metal deposition process and increase the quality of the metal deposited. In one embodiment, a copper deposition proc... | 11/17/2009 |
| 7608535 | Method for forming metal contact in semiconductor device An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the lower wiring layer is formed by etching the interlayer insulation film. ... | 10/27/2009 |
| 7582558 | Reducing corrosion in copper damascene processes Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer... | 09/01/2009 |
| 7524756 | Process of forming a semiconductor assembly having a contact structure and contact liner A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a cond... | 04/28/2009 |
| 7514354 | Methods for forming damascene wiring structures having line and plug conductors formed from different materials Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor... | 04/07/2009 |
| 7504334 | Semiconductor device and method for manufacturing same Embodiments relate to a semiconductor device and a manufacturing method thereof. In embodiments, the semiconductor device may include a semiconductor substrate formed thereon with a first metal line, a PMD (pre metal dielectric) layer formed on the semiconductor sub... | 03/17/2009 |
| 7494919 | Method for post lithographic critical dimension shrinking using thermal reflow process A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer,... | 02/24/2009 |
| 7494920 | Method of fabricating a vertically mountable IC package A method of fabricating a vertically mountable integrated circuit (IC) package is presented. An integrated circuit is mounted on a printed circuit board (PCB) and electrically coupled to a bond pad on the PCB. The bond pad is coupled with a via that is embedded in t... | 02/24/2009 |
| 7482264 | Method of forming metal line of semiconductor device, and semiconductor device A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over ... | 01/27/2009 |
| 7473639 | Method of forming dual damascene pattern Disclosed is a method of forming a dual damascene pattern. The method can include forming a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a cap insulating layer on a substrate, forming a preliminary via hole... | 01/06/2009 |
| 7468318 | Method for manufacturing mold type semiconductor device A method for manufacturing a mold type semiconductor device is provided. The device includes a semiconductor chip having a semiconductor part and a metallic member connecting to the chip via a conductive layer and a connecting member. The method includes: forming th... | 12/23/2008 |
| 7456094 | LDMOS transistor A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insu... | 11/25/2008 |
| 7452805 | Aluminum based conductor for via fill and interconnect A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm2 and a PVD aluminum base conductor filled in the opening. ... | 11/18/2008 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7432199 | Method of fabricating semiconductor device having reduced contact resistance Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After ... | 10/07/2008 |
| 7422978 | Methods of manufacturing interposers with flexible solder pad elements Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer... | 09/09/2008 |
