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| Number | Title | Issue Date |
| 8021976 | Method of wire bonding over active area of a semiconductor circuit A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metall... | 09/20/2011 |
| 7951705 | Multilayered cap barrier in microelectronic interconnect structures Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to... | 05/31/2011 |
| 7910476 | Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus ... | 03/22/2011 |
| 7863182 | Dicing die-bonding film The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer (2) on a substrate material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein the adhesion of the p... | 01/04/2011 |
| 7838414 | Method for manufacturing semiconductor device utilizing low dielectric layer filling gaps between metal lines A semiconductor device is manufactured by forming a low dielectric constant layer on a semiconductor substrate which is formed with metal lines; implementing primary ultraviolet treatment of the low dielectric constant layer; forming a capping layer on the low diele... | 11/23/2010 |
| 7666782 | Wire structure and forming method of the same A wire structure, having: a first insulating layer having a lower layer trench formed in an outer surface thereof; a first diffusion preventing film formed on an inner surface of the lower layer trench; a lower layer wire filled in the lower layer trench over the fi... | 02/23/2010 |
| 7611985 | Formation of holes in substrates using dewetting coatings Methods and systems for forming holes in a substrate using dewetting coating are described herein. ... | 11/03/2009 |
| 7541280 | Method of foming a micromechanical structure A method of forming a micromechanical structure, wherein at least one micromechanical structural layer is provided above a substrate. The micromechanical structural layer is sustained between a lower sacrificial silicon layer and an upper sacrificial silicon layer, ... | 06/02/2009 |
| 7494918 | Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an... | 02/24/2009 |
| 7476610 | Removable spacer A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that depos... | 01/13/2009 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7427561 | Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; fo... | 09/23/2008 |
| 7422977 | Copper adhesion improvement device and method A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper... | 09/09/2008 |
| 7419855 | Apparatus and method for miniature semiconductor packages A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent th... | 09/02/2008 |
| 7405153 | Method for direct electroplating of copper onto a non-copper plateable layer A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein th... | 07/29/2008 |
| 7405152 | Reducing wire erosion during damascene processing A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby str... | 07/29/2008 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad a... | 05/06/2008 |
| 7358589 | Amorphous carbon metal-to-metal antifuse with adhesion promoting layers A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting lay... | 04/15/2008 |
| 7354853 | Selective dry etching of tantalum and tantalum nitride The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which pass... | 04/08/2008 |
| 7352021 | Magnetic random access memory devices having titanium-rich lower electrodes with oxide layer and oriented tunneling barrier Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed p... | 04/01/2008 |
| 7351655 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/01/2008 |
| 7348617 | Semiconductor device A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric... | 03/25/2008 |
| 7344976 | Method for fabricating nonvolatile semiconductor memory device An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conducti... | 03/18/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7335282 | Sputtering using an unbalanced magnetron A sputtering process and magnetron especially advantageous for low-pressure plasma sputtering or sustained self-sputtering, in which the magnetron has a reduced area but full target coverage. The magnetron includes an outer pole face surrounding an inner pole face w... | 02/26/2008 |
| 7332383 | Switching device for a pixel electrode and methods for fabricating the same The invention discloses a switching device for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A buffer layer is formed between the gate and the substrate, and/... | 02/19/2008 |
| 7323419 | Method of fabricating semiconductor device A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, perfo... | 01/29/2008 |
| 7323387 | Method to make nano structure below 25 nanometer with high uniformity on large scale A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques. ... | 01/29/2008 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7300866 | Method for fabricating metal line in a semiconductor A metal line is fabricated in a semiconductor device by a method including: forming an etch stop layer on a substrate; forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer including dual damascene patterns, each respectively... | 11/27/2007 |
| 7300860 | Integrated circuit with metal layer having carbon nanotubes and methods of making same A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution. ... | 11/27/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7285858 | Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first ... | 10/23/2007 |
| 7285842 | Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration Structures employing siloxane epoxy polymers as diffusion barriers adjacent conductive metal layers are disclosed. The siloxane epoxy polymers exhibit excellent adhesion to conductive metals, such as copper, and provide an increase in the electromigration lifetime o... | 10/23/2007 |
| 7282447 | Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect... | 10/16/2007 |
| 7271099 | Forming a conductive pattern on a substrate A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conduc... | 09/18/2007 |
| 7271087 | Dual damascene interconnection in semiconductor device and method for forming the same A dual damascene interconnection in a semiconductor device is formed to be capable of preventing fluorine (F) component from being diffused through sidewalls of a via hole and a trench. The dual damascene interconnection includes a lower metal interconnection film, ... | 09/18/2007 |
| 7265048 | Reduction of copper dewetting by transition metal deposition A method and apparatus for forming layers on a substrate comprising depositing a metal seed layer on a substrate surface having apertures, depositing a transition metal layer over the copper seed layer, and depositing a bulk metal layer over the transition metal lay... | 09/04/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
