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| Number | Title | Issue Date |
| 8105934 | Bump structure for a semiconductor device and method of manufacture A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, ... | 01/31/2012 |
| 8101514 | Semiconductor device having elastic solder bump to prevent disconnection Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection re... | 01/24/2012 |
| 8076233 | Method of forming electrode connecting portion A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating rol... | 12/13/2011 |
| 8039385 | IC devices having TSVS including protruding tips having IMC blocking tip ends A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a porti... | 10/18/2011 |
| 8034704 | Method for manufacturing semiconductor device and semiconductor device A method for manufacturing a semiconductor device includes the steps of providing an element forming layer on a first surface of a semiconductor substrate, and providing an external connection terminal on a second surface of the semiconductor substrate opposite to t... | 10/11/2011 |
| 8026163 | Manufacturing method of semiconductor integrated circuit device When relatively hard Au bump electrodes are mass-produced by electrolytic plating while ensuring usually required properties such as a non-glossy property and shape-flatness, combination of conditions, such as low liquid temperature, high current density, and low co... | 09/27/2011 |
| 8008182 | Semiconductor device and method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes: a) preparing a structure including a semiconductor substrate, an electrode provided on a first surface of the semiconductor substrate, and an insulation film provided on the first surface and having an open... | 08/30/2011 |
| 7985672 | Solder ball attachment ring and method of use A method of attaching a solder ball to a bonding pad includes disposing flux on the bonding pad, attaching a conductive metal ring to the pad using the flux, and placing the solder ball in the ring. A reflow operation is performed that secures the ring to the pad an... | 07/26/2011 |
| 7968445 | Semiconductor package with passivation island for reducing stress on solder bumps A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is forme... | 06/28/2011 |
| 7960272 | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations... | 06/14/2011 |
| 7951700 | Flip chip mounting method and bump forming method The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic co... | 05/31/2011 |
| 7951701 | Semiconductor device having elastic solder bump to prevent disconnection Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection re... | 05/31/2011 |
| 7951699 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so tha... | 05/31/2011 |
| 7932170 | Flip chip bump structure and fabrication method A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned... | 04/26/2011 |
| 7927998 | Plating method, semiconductor device fabrication method and circuit board fabrication method The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 | 04/19/2011 |
| 7919406 | Structure and method for forming pillar bump structure having sidewall protection A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above th... | 04/05/2011 |
| 7906424 | Conductor bump method and apparatus Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a sur... | 03/15/2011 |
| 7884007 | Super high density module with integrated wafer level packages A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packa... | 02/08/2011 |
| 7879714 | Semiconductor device manufacturing method There is provide a semiconductor device manufacturing method, including: preparing a substrate; laminating an insulation layer on the substrate; laminating a first underlying metal layer on the insulation layer; forming rewiring on the first underlying metal layer; ... | 02/01/2011 |
| 7871918 | Manufacturing method of contact structure A manufacturing method of a contact structure includes first providing a substrate on which a contact pad has already been formed. Afterwards, a polymer bump is formed on the contact pad. Next, a conductive layer is formed on the polymer bump. The conductive layer c... | 01/18/2011 |
| 7871917 | Semiconductor device and manufacturing method for the same To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged ... | 01/18/2011 |
| 7867888 | Flip-chip package substrate and a method for fabricating the same The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer c... | 01/11/2011 |
| 7855136 | Method of mounting semiconductor chip to circuit substrate using solder bumps and dummy bumps A semiconductor chip comprises a silicon substrate on which semiconductor elements are formed, pads, each of which is formed on the silicon substrate and electrically connected to at least one of the semiconductor elements, a first insulating layer having an opening... | 12/21/2010 |
| 7851346 | Bonding metallurgy for three-dimensional interconnect A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second... | 12/14/2010 |
| 7846829 | Stacked solder balls for integrated circuit device packaging and assembly A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of th... | 12/07/2010 |
| 7842598 | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12... | 11/30/2010 |
| 7842597 | Chip package, chip packaging, chip carrier and process thereof A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductiv... | 11/30/2010 |
| 7833897 | Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface A method is provided for making of interconnect solder bumps on a wafer or other electronic device without depositing any significant amount of tin or other solder component from the solder onto the wafer surface which tin can cause shorts or other defects in the wa... | 11/16/2010 |
| 7820543 | Enhanced copper posts for wafer level chip scale packaging An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. Th... | 10/26/2010 |
| 7816250 | Composite solder TIM for electronic package A method includes providing a mixture of molten indium and molten aluminum, and agitating the mixture while reducing its temperature until the aluminum changes from liquid phase to solid phase, forming particles distributed within the molten indium. Agitation of the... | 10/19/2010 |
| 7816251 | Formation of circuitry with modification of feature height A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts. ... | 10/19/2010 |
| 7795127 | Electronic device manufacturing method and electronic device There are provided the steps of forming a bump 104 having a protruded portion 104B on an electrode pad 103 formed on a substrate 101A, forming an insulating layer 105 on the substrate 101A and exposing a part of the protrude... | 09/14/2010 |
| 7790598 | System, apparatus, and method for advanced solder bumping According to some embodiments, a method, apparatus, and system are provided. In some embodiments, the method includes providing solder resist material on a surface of a substrate, applying mask material on top of the solder resist material, reflowing solder located ... | 09/07/2010 |
| 7790595 | Manufacturing method improving the reliability of a bump electrode A method for manufacturing a semiconductor device comprises (a) forming a resin layer that includes at least a plurality of a first and a second resin parts, being separated from each other, over a semiconductor substrate having an electrode pad and a passivation fi... | 09/07/2010 |
| 7790596 | Apparatus and method for semiconductor wafer bumping via injection molded solder An improved apparatus for positioning and aligning a patterned surface of a semiconductor structure directly opposite to solder filled patterned mold cavities of a mold structure includes a pattern based alignment too including means for identifying a mold training ... | 09/07/2010 |
| 7790597 | Solder cap application process on copper bump using solder powder film A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adher... | 09/07/2010 |
| 7786001 | Electrical interconnect structure and method An electrical structure and method of forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mech... | 08/31/2010 |
| 7781325 | Copper pillar tin bump on semiconductor chip and method of forming the same Copper pillar tin bump on semiconductor chip comprises a copper layer composed on chip and a tin layer entirely wrapping whole outer surface of said copper layer. A method for forming of the copper pillar tin bump on semiconductor chip comprises: composing the first... | 08/24/2010 |
| 7767574 | Method of forming micro metal bump The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate. The method... | 08/03/2010 |
| 7732319 | Interconnection structure of integrated circuit chip An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer ... | 06/08/2010 |
