Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 8173532 | Semiconductor transistors having reduced distances between gate electrode regions A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpen... | 05/08/2012 |
| 8168520 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device according to an embodiment of the present invention forms at least one pair of gate electrodes having end portions opposed to each other across a gap. The method includes forming a gate insulator and a gate electrode ... | 05/01/2012 |
| 8138075 | Systems and methods for the manufacture of flat panel devices A backplane having a circuit array having at least one region comprising a substrate having a conductive plane under a dielectric surface, a first conductive layer on said dielectric surface, a selectively disposed insulator disposed over said first conductive layer... | 03/20/2012 |
| 8124512 | Methods of forming integrated circuit devices having different gate electrode cross sections A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resis... | 02/28/2012 |
| 8088679 | Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion regi... | 01/03/2012 |
| 8088681 | Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode le... | 01/03/2012 |
| 8088682 | Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacen... | 01/03/2012 |
| 8088680 | Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The cell layout also includes a gate electrode level layout defined to include linear-sh... | 01/03/2012 |
| 8058160 | Method of forming nonvolatile memory device A method of forming the gate patterns of a nonvolatile memory device comprises stacking a gate insulating layer and a first conductive layer over a semiconductor substrate; forming isolation hard mask patterns over the first conductive layer; etching the first condu... | 11/15/2011 |
| 8053346 | Semiconductor device and method of forming gate and metal line thereof with dummy pattern and auxiliary pattern A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. T... | 11/08/2011 |
| 8030196 | Transistor formation using capping layer A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transist... | 10/04/2011 |
| 8003506 | Single poly CMOS imager More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge... | 08/23/2011 |
| 7977226 | Flash memory device and method of fabricating the same A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low tempe... | 07/12/2011 |
| 7960266 | Spacer patterns using assist layer for high density semiconductor devices High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable e... | 06/14/2011 |
| 7955964 | Dishing-free gap-filling with multiple CMPs A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, whe... | 06/07/2011 |
| 7871912 | Methods of making semiconductor-based electronic devices by forming freestanding semiconductor structures Various methods for forming active electronic devices, such as field-effect transistors, and devices made using these methods are disclosed. Some of the methods include growing freestanding nano-, micro- and milli-scale semiconducting structures that are used for th... | 01/18/2011 |
| 7838404 | Method of fabricating a nonvolatile semiconductor memory A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and... | 11/23/2010 |
| 7781321 | Electroless metal deposition for dual work function The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric l... | 08/24/2010 |
| 7772102 | Nonvolatile semiconductor memory and fabrication method for the same A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region. The nonvolatile semiconductor memory includes a ... | 08/10/2010 |
| 7767567 | Method of forming a semiconductor memory device and semiconductor memory device Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is appli... | 08/03/2010 |
| 7759235 | Semiconductor device manufacturing methods Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed ... | 07/20/2010 |
| 7737016 | Two-print two-etch method for enhancement of CD control using ghost poly According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate. The disclosed methods can be incorporated into, for example, altPSM, attPSM, and binary lithographic met... | 06/15/2010 |
| 7732316 | Method for manufacturing a semiconductor device In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal... | 06/08/2010 |
| 7700471 | Methods of making semiconductor-based electronic devices on a wire and articles that can be made thereby Strands active electronic devices (AEDs), such as field-effect transistors, are made by processing a semiconductor substrate so that it yields a number of elongate semiconductor members liberated from the starting substrate. The elongate semiconductor members are se... | 04/20/2010 |
| 7645692 | Semiconductor device and method of manufacturing the same In one embodiment of the present invention, provided is a semiconductor device having a silicon substrate provided with a DRAM region containing first transistors and capacitor elements, and with a logic region containing second transistors. A minimum gate length of... | 01/12/2010 |
| 7638416 | Methods of making semiconductor-based electronic devices on a wire and articles that can be made using such devices Strands of active electronic devices (AEDs), such as FETs, are made by first completely or partially forming a plurality of the AEDs on a precursor substrate. Then, one or more elongate conductors (e.g., wires) are secured to ones of the AEDs so as to electrically c... | 12/29/2009 |
| 7601622 | Method of forming fine patterns in semiconductor device and method of forming gate using the same There are provided a method of forming fine patterns in a semiconductor device, and a method of forming a gate with a fine critical dimension using the same. In the method of forming fine patterns in a semiconductor device, a plurality of sidewall buffer patterns ar... | 10/13/2009 |
| 7582548 | Semiconductor device and manufacturing method thereof A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate a... | 09/01/2009 |
| 7557024 | Single poly CMOS imager More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge... | 07/07/2009 |
| 7547622 | Fabrication of CCD image sensors using single layer polysilicon A method for fabricating CCD imaging structures is disclosed, comprising the steps of providing a silicon substrate; growing a dielectric layer substantially overlying the silicon substrate; depositing a first layer of polysilicon substantially overlaying the dielec... | 06/16/2009 |
| 7510954 | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Select... | 03/31/2009 |
| 7473624 | Method for manufacturing semiconductor device There is provided a method for manufacturing the semiconductor device for obtaining capacitance characteristics of a larger capacitance and delay characteristics with higher efficiency. An embodiment according to the present invention employs the configuration of fo... | 01/06/2009 |
| 7442598 | Method of forming an interlayer dielectric A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over t... | 10/28/2008 |
| 7427544 | Semiconductor device and method of manufacturing the same A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stoppe... | 09/23/2008 |
| 7422970 | Method for modifying circuit within substrate A method is provided for modifying a circuit containing a plurality of electrodes, within a substrate, comprising the steps of: (a) selecting at least two electrodes for making a connection; (b) removing materials covering the electrodes with a focused ion beam (FIB... | 09/09/2008 |
| 7416971 | Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used... | 08/26/2008 |
| 7410855 | Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f... | 08/12/2008 |
| 7390749 | Self-aligned pitch reduction A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a se... | 06/24/2008 |
| 7378311 | Method of forming memory cells in an array The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first ac... | 05/27/2008 |
| 7371667 | Semiconductor device and method of fabricating same There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/d... | 05/13/2008 |
