Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8187962 | Self aligned silicided contacts Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed ov... | 05/29/2012 |
| 8187963 | Method of forming back contact to a cadmium telluride solar cell A method of forming an ohmic contact to a surface of a Cd and Te containing compound film as may be found, for example in a photovoltaic cell. The method comprises forming a Te-rich layer on the surface of the Cd and Te containing compound film; depositing an interf... | 05/29/2012 |
| 8183139 | Reduced defectivity in contacts of a semiconductor device comprising replacement gate electrode structures by using an intermediate cap layer Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created ... | 05/22/2012 |
| 8143152 | Manufacturing method of semiconductor device having self-aligned contact connected to silicide layer on substrate surface A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108... | 03/27/2012 |
| 8138074 | ICs with end gates having adjacent electrically connected field poly A method of forming an IC includes forming a first and a second gate portion using a poly mask. The first portion includes a first active poly gate having a line width W1 over an end of a first active area framed by a first active area edge and a first ad... | 03/20/2012 |
| 8088678 | Semiconductor manufacturing apparatus and method A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the tre... | 01/03/2012 |
| 8084344 | Methods of fabricating a semiconductor device A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on ... | 12/27/2011 |
| 8080468 | Methods for fabricating passivated silicon nanowires and devices thus obtained Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MO... | 12/20/2011 |
| 8076230 | Method of forming self-aligned contacts and local interconnects A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the perip... | 12/13/2011 |
| 8003505 | Image sensor and method of fabricating the same A method of fabricating an image sensor. A method of fabricating an image sensor may include preparing a substrate including a pixel region and/or a logic region having transistors and/or gates. A method of fabricating an image sensor may include forming a first int... | 08/23/2011 |
| 7932166 | Field effect transistor having a stressed contact etch stop layer with reduced conformality By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD technique... | 04/26/2011 |
| 7897499 | Method for fabricating a semiconductor device with self-aligned contact A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, fil... | 03/01/2011 |
| 7888252 | Self-aligned contact A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, fi... | 02/15/2011 |
| 7884004 | Maskless process for suspending and thinning nanowires Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configurati... | 02/08/2011 |
| 7884005 | Method of manufacturing a semiconductor device Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second ga... | 02/08/2011 |
| 7879707 | Semiconductor integrated circuit device and related method Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circu... | 02/01/2011 |
| 7846825 | Method of forming a contact hole and method of manufacturing a semiconductor device having the same In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed... | 12/07/2010 |
| 7842593 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess havi... | 11/30/2010 |
| 7767566 | Flash memory device and method of forming the device Cell gate patterns including first portions separated from each other with a first distance and second portions separated from each other with a second distance less than the first distance, and spacers are formed both sidewalls of the pair of cell gate patterns. Th... | 08/03/2010 |
| 7737015 | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transis... | 06/15/2010 |
| 7718520 | Semiconductor integrated circuit device and related method Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circu... | 05/18/2010 |
| 7713855 | Method for forming bit-line contact plug and transistor structure A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask l... | 05/11/2010 |
| 7709366 | Semiconductor device and method of manufacturing the same A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silic... | 05/04/2010 |
| 7696074 | Method of manufacturing NAND flash memory device A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor su... | 04/13/2010 |
| 7655548 | Programmable power management using a nanotube structure Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integra... | 02/02/2010 |
| 7615475 | Method for fabricating landing polysilicon contact structures for semiconductor devices A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilico... | 11/10/2009 |
| 7575990 | Method of forming self-aligned contacts and local interconnects A method of forming a plurality of self-aligned contacts of a core region and local interconnect openings of a peripheral region of a semiconductor device is disclosed. A plurality of gate-structures are formed on the core and peripheral regions of a semiconductor s... | 08/18/2009 |
| 7572721 | Method of forming a semiconductor device having an etch stop layer and related device In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielec... | 08/11/2009 |
| 7553748 | Semiconductor device and method of manufacturing the same According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interl... | 06/30/2009 |
| RE40790 | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wher... | 06/23/2009 |
| 7538017 | Method of manufacturing a thin film transistor, a thin film transistor manufactured by the method, a method of manufacturing flat panel display device, and a flat panel display device manufactured by the method Provided are a method of manufacturing a plastic substrate having a TFT, a substrate manufactured thereby, a method of manufacturing a flat panel display device, and a flat display device manufactured thereby, which can be used for a flexible flat display device. Th... | 05/26/2009 |
| 7528059 | Method for reducing polish-induced damage in a contact structure by forming a capping layer By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Conseq... | 05/05/2009 |
| 7432182 | Semiconductor device and method for manufacturing the same An exemplary method for manufacturing a semiconductor device includes: forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer, respectively formed thereabove and one or more junction regions formed therein so ... | 10/07/2008 |
| 7427546 | Transistor device and method for manufacturing the same A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located ove... | 09/23/2008 |
| 7422942 | Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ... | 09/09/2008 |
| 7419896 | Method for forming landing plug contact in semiconductor device A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over t... | 09/02/2008 |
| 7419895 | NAND memory arrays Methods and apparatus are provided. A source slot and a drain contact region are formed at opposite ends of a NAND string disposed on a substrate of a NAND memory array using a single mask. The drain contact region is self-aligned to a drain select gate. The NAND st... | 09/02/2008 |
| 7411251 | Self protecting NLDMOS, DMOS and extended voltage NMOS devices In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an ... | 08/12/2008 |
| 7387919 | Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern ... | 06/17/2008 |
| 7381617 | Method of fabricating flash memory device A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barri... | 06/03/2008 |
