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| Number | Title | Issue Date |
| 8349718 | Self-aligned silicide formation on source/drain through contact via According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film for... | 01/08/2013 |
| 8247319 | Method to enable the process and enlarge the process window for silicide, germanide or germanosilicide formation in structures with extremely small dimensions Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having e... | 08/21/2012 |
| 8101511 | Method of manufacturing a junction barrier Schottky diode with dual silicides An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is o... | 01/24/2012 |
| 8008177 | Method for fabricating semiconductor device using a nickel salicide process A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the g... | 08/30/2011 |
| 7981784 | Methods of manufacturing a semiconductor device Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silici... | 07/19/2011 |
| 7943499 | FUSI integration method using SOG as a sacrificial planarization layer A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG ... | 05/17/2011 |
| 7803702 | Method for fabricating MOS transistors A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substra... | 09/28/2010 |
| 7749877 | Process for forming Schottky rectifier with PtNi silicide Schottky barrier A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film ... | 07/06/2010 |
| 7732313 | FUSI integration method using SOG as a sacrificial planarization layer A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG ... | 06/08/2010 |
| 7732312 | FUSI integration method using SOG as a sacrificial planarization layer A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG ... | 06/08/2010 |
| 7662707 | Method of forming relatively continuous silicide layers for semiconductor devices Methods of forming metal silicide layers in a semiconductor device are provided in which a first metal silicide layer may be formed on a substrate, where the first metal silicide layer comprises a plurality of fragments of a metal silicide that are separated by one ... | 02/16/2010 |
| 7566642 | Process of manufacturing an N-type Schottky barrier tunnel transistor An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in ... | 07/28/2009 |
| 7550372 | Method of fabricating conductive lines with silicide layer A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the ... | 06/23/2009 |
| 7501333 | Work function adjustment on fully silicided (FUSI) gate A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second... | 03/10/2009 |
| 7432180 | Method of fabricating a nickel silicide layer by conducting a thermal annealing process in a silane gas A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nic... | 10/07/2008 |
| 7432181 | Method of forming self-aligned silicides A method of forming self-aligned silicides is described and applied to a substrate having an isolation area, which divides the substrate into a first area and a second area. A resist protective oxide layer is formed on the substrate, and subsequently a mask layer is... | 10/07/2008 |
| 7429525 | Fabrication process of a semiconductor device A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing... | 09/30/2008 |
| 7425482 | Non-volatile memory device and method for fabricating the same A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer c... | 09/16/2008 |
| 7396764 | Manufacturing method for forming all regions of the gate electrode silicided The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semico... | 07/08/2008 |
| 7372152 | Copper interconnect systems An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 05/13/2008 |
| 7368371 | Silicon carbide Schottky diode and method of making the same A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is forme... | 05/06/2008 |
| 7351655 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/01/2008 |
| 7348233 | Methods for fabricating a CMOS device including silicide contacts Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode ov... | 03/25/2008 |
| 7348265 | Semiconductor device having a silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located ov... | 03/25/2008 |
| 7341933 | Method for manufacturing a silicided gate electrode using a buffer layer The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode ( | 03/11/2008 |
| 7338815 | Semiconductor device manufacturing method A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the... | 03/04/2008 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, ... | 03/04/2008 |
| 7306983 | Method for forming dual etch stop liner and protective layer in a semiconductor device The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use i... | 12/11/2007 |
| 7297618 | Fully silicided gate electrodes and method of making the same The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are... | 11/20/2007 |
| 7291524 | Schottky-barrier mosfet manufacturing method using isotropic etch process A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the m... | 11/06/2007 |
| 7285491 | Salicide process A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second ste... | 10/23/2007 |
| 7268024 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is... | 09/11/2007 |
| 7247549 | Manufacturing method for semiconductor device having a T type gate electrode This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilic... | 07/24/2007 |
| 7235471 | Method for forming a semiconductor device having a silicide layer A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating layer over the semiconductor substrate, forming a conductive layer over the insulating layer, forming a first metal silicide layer over the conductive lay... | 06/26/2007 |
| 7223689 | Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the ... | 05/29/2007 |
| 7208398 | Metal-halogen physical vapor deposition for semiconductor device defect reduction The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130)... | 04/24/2007 |
| 7199032 | Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater... | 04/03/2007 |
| 7183182 | Method and apparatus for fabricating CMOS field effect transistors A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation,... | 02/27/2007 |
| 7172933 | Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate... | 02/06/2007 |
| 7172955 | Silicon composition in CMOS gates A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSix film formed on the first gate insulating film, where M represents a metal element selected from tungsten and mol... | 02/06/2007 |
