Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 7842591 | Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist... | 11/30/2010 |
| 7575989 | Method of manufacturing a transistor of a semiconductor device A method of manufacturing a transistor in which gate resistance is lowered and short channel effects are controlled by forming a trench-type gate. The threshold voltage can also be more tightly controlled. ... | 08/18/2009 |
| 7553747 | Schottky diode having a nitride semiconductor material and method for fabricating the same A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first nitride semiconductor layer and having a different conductivity type from that of the first nitride semicondu... | 06/30/2009 |
| 7439166 | Method for producing tiered gate structure devices In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening... | 10/21/2008 |
| 7419894 | Gate electrode and manufacturing method thereof, and semiconductor device and manufacturing method thereof The present invention provides a method of manufacturing a gate electrode in which a fine gate electrode can effectively be manufactured by thickening a resist opening for gate electrodes formed by ordinary electron beam lithography so as to reduce opening dimension... | 09/02/2008 |
| 7387955 | Field effect transistor and method for manufacturing the same A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and... | 06/17/2008 |
| 7345001 | Gate dielectric having a flat nitrogen profile and method of manufacture therefor The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielec... | 03/18/2008 |
| 7300880 | Methods for forming fine photoresist patterns A method of forming a fine pattern by a tri-layer resist process to overcome a bi-layer resist process is disclosed. When a fine pattern is formed using a silicon photoresist, a gas protection film is coated on a photoresist to prevent exhaustion of silicon gas gene... | 11/27/2007 |
| 7223645 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 05/29/2007 |
| 7217968 | Recessed gate for an image sensor A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surfa... | 05/15/2007 |
| 7157383 | Method for forming silicon dioxide film on silicon substrate, method for forming oxide film on semiconductor substrate, and method for producing semiconductor device After cleaning a surface of a silicon substrate (1), impurities and natural oxide film existing on the silicon substrate (1) are removed by soaking the silicon substrate (1) in a 0.5%-by-volume HF aqueous solution for 5 minutes. The silicon subs... | 01/02/2007 |
| 7141464 | Method of fabricating T-type gate Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the sec... | 11/28/2006 |
| 7118779 | Reactor surface passivation through chemical deactivation Protective layers are formed on a surface of an atomic layer deposition (ALD) or chemical vapor deposition (CVD) reactor. Parts defining a reaction space for an ALD or CVD reactor can be treated, in situ or ex situ, with chemicals that deactivate reactive sites on t... | 10/10/2006 |
| 7115921 | Nano-scaled gate structure with self-interconnect capabilities Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically co... | 10/03/2006 |
| 7084021 | Method of forming a structure wherein an electrode comprising a refractory metal is deposited The presently disclosed technology provides a method for forming a structure wherein an electrode, such as a gate, comprising a refractory metal is deposited. The method comprises depositing a plurality of electron sensitive resist layers on the substrate. Several o... | 08/01/2006 |
| 7037771 | CMOS imager with a self-aligned buried contact An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from th... | 05/02/2006 |
| 7018548 | Conductive thin film pattern and method of forming the same, method of manufacturing thin film magnetic head, method of manufacturing thin film inductor, and method of manufacturing micro device A high-precision conductive thin film pattern having a high aspect ratio and a method of forming the same are provided. Further, a method of manufacturing a thin film magnetic head, a thin film inductor, and a micro device each including such a conductive thin film ... | 03/28/2006 |
| 7012286 | Heterojunction field effect transistor A heterojunction field effect transistor operative from the micro wave band to the millimeter wave band has a gate recess structure formed in a manner such that its eye-empty areas have a significant effect on the voltage durability of the transistor. The eye-empty ... | 03/14/2006 |
| 6979634 | Manufacturing method for semiconductor device having a T-type gate electrode This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilic... | 12/27/2005 |
| 6884669 | Hatted polysilicon gate structure for improving salicide performance and method of forming the same Alternate methods of forming low resistance “hatted” polysilicon gate elements are provided that increase the effective area in the polysilicon gate for silicide grain growth during silicide formation. The expanded top portion helps to prevent silicide agglomera... | 04/26/2005 |
| 6784036 | Method for making semiconductor device A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a ... | 08/31/2004 |
| 6784081 | Gate structure forming method of field effect transistor A method of forming a gate structure includes forming sequentially a pad layer and a first photoresist layer over a substrate. A cross-linked surface layer is formed on the surface of the first photoresist layer, followed by rounding the profile of the first photore... | 08/31/2004 |
| 6780694 | MOS transistor A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrod... | 08/24/2004 |
| 6780738 | PATTERN FORMING METHOD, METHOD OF MAKING MICRODEVICE, METHOD OF MAKING THIN-FILM MAGNETIC HEAD, METHOD OF MAKING MAGNETIC HEAD SLIDER, METHOD OF MAKING MAGNETIC HEAD APPARATUS, AND METHOD OF MAKING MAGNETIC RECORDING AND REPRODUCING APPARATUS All the electrode films corresponding to respective metal materials are laminated on a substrate beforehand, a first electrode film located farthest from the substrate is formed with a first metal pattern suitable for the first electrode film, and then the first ele... | 08/24/2004 |
| 6767811 | CMOS imager with a self-aligned buried contact An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from th... | 07/27/2004 |
| 6743737 | Method of improving moisture resistance of low dielectric constant films A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10 W to about 500 W, exposing the silicon... | 06/01/2004 |
| 6730586 | Semiconductor device having an overhanging structure and method for fabricating the same An edge of a passivation film is positioned inside an edge of an overhanging emitter structure by a distance L so that a base electrode layer is formed at an interval not to overlap the edge of the passivation film even when the base electrode layer is formed by etc... | 05/04/2004 |
| 6566282 | Method of forming a silicon oxide layer A silicon oxide layer is formed on a semiconductor wafer by performing a high temperature oxidation (HTO) process using dichlorosilane (SiH2 Cl2) and nitrous oxide (N2 O), as reacting gases, having a flow rates with a rati... | 05/20/2003 |
| 6534351 | Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-ov... | 03/18/2003 |
| 6531380 | Method of fabricating T-shaped recessed polysilicon gate transistors A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in ... | 03/11/2003 |
| 6524937 | Selective T-gate process A process of simultaneously forming a plurality of metal features on a substrate, in which at least one metal feature has undercut sides and at least one metal feature does not have undercut sides involves the application of a lower photoresist feature ha... | 02/25/2003 |
| 6509252 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes an exposing step of transferring a support pattern onto an non-exposed area of a resist layer so that an opening for forming a support is formed in a thick part of the resist layer. The support is ... | 01/21/2003 |
| 6509253 | T-shaped gate electrode for reduced resistance An integrated circuit includes a transistor with a T-shaped gate conductor. The T-shaped gate conductor can achieve a lower sheet resistance characteristic. The transistor can include a silicided source region, a silicided drain region, and a gate structu... | 01/21/2003 |
| 6495434 | CMOS imager with a self-aligned buried contact An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leak... | 12/17/2002 |
| 6483135 | Field effect transistor A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source el... | 11/19/2002 |
| 6417036 | Method of fabricating dynamic random access memories An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact ... | 07/09/2002 |
| 6403456 | T or T/Y gate formation using trim etch processing A method for fabricating a T-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second ... | 06/11/2002 |
| 6392278 | Fet having a reliable gate electrode A comb-shape MESFET has a gate electrode having a plurality of gate fingers coupled to a gate bar at the proximal ends of the gate fingers. The distal end of each gate finger is formed as a large width end on the inactive region of the wafer. The large wi... | 05/21/2002 |
| 6387783 | Methods of T-gate fabrication using a hybrid resist Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist lay... | 05/14/2002 |
| 6372613 | Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertica... | 04/16/2002 |
