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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 7439166 | Method for producing tiered gate structure devices In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening... | 10/21/2008 |
| 7354781 | Method of manufacturing field emission device A method of manufacturing a field emission device (FED) using a photoresist for performing multi-patterning processes, whereby different structures can be multi-patterned using a single photoresist mask. The photoresist has a solubility to a solvent by post-exposure... | 04/08/2008 |
| 7339273 | Semiconductor device with a via hole having a diameter at the surface larger than a width of a pad electrode The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surfac... | 03/04/2008 |
| 7262070 | Method to make a weight compensating/tuning layer on a substrate Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick... | 08/28/2007 |
| 7229745 | Lithographic semiconductor manufacturing using a multi-layered process Multilayer resist systems and techniques used for liftoff or planarizing topography wherein the dimensions and thicknesses of the layers are independently controlled. The undercut may also be independently controlled for precision structures. ... | 06/12/2007 |
| 7184850 | System and method for allocating multi-function resources for a wetdeck process in semiconductor wafer fabrication A system and method is disclosed for allocating multi-function resources among a plurality of tasks within a wetdeck process in semiconductor wafer fabrication. A resource allocator allocates multi-function resources among tasks within a process system that executes... | 02/27/2007 |
| 7132358 | Method of forming solder bump with reduced surface defects A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a ... | 11/07/2006 |
| 7129590 | Stencil and method for depositing material onto a substrate A stencil and method for depositing a coupon of underfill material onto a substrate that is to receive an integrated circuit die. ... | 10/31/2006 |
| 7041541 | Method for producing a semiconductor component, and semiconductor component produced by the same A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode. ... | 05/09/2006 |
| 7008810 | Method for fabricating at least one mesa or ridge structure or at least one electrically pumped region in a layer or layer sequence A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for defi... | 03/07/2006 |
| 6959225 | Graphical user interface for allocating multi-function resources in semiconductor wafer fabrication and method of operation A system and method is disclosed for allocating multi-function resources among a plurality of tasks within a process system in semiconductor wafer fabrication. A resource allocator allocates multi-function resources among tasks within a process system that executes ... | 10/25/2005 |
| 6929958 | Method to make small isolated features with pseudo-planarization for TMR and MRAM applications A method for forming small, isolated device structures by photolithography, utilizing overlapping bi-layer suspension-bridge shaped photomasks. The use of a suspended mask to define a device shape beneath it eliminates the problems associated with uneven undercuttin... | 08/16/2005 |
| 6887792 | Embossed mask lithography Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transpare... | 05/03/2005 |
| 6784081 | Gate structure forming method of field effect transistor A method of forming a gate structure includes forming sequentially a pad layer and a first photoresist layer over a substrate. A cross-linked surface layer is formed on the surface of the first photoresist layer, followed by rounding the profile of the first photore... | 08/31/2004 |
| 6720200 | Field effect transistor and fabrication process thereof Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing... | 04/13/2004 |
| 6524937 | Selective T-gate process A process of simultaneously forming a plurality of metal features on a substrate, in which at least one metal feature has undercut sides and at least one metal feature does not have undercut sides involves the application of a lower photoresist feature ha... | 02/25/2003 |
| 6492214 | Method of fabricating an insulating layer A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconducto... | 12/10/2002 |
| 6204102 | Method of fabricating compound semiconductor devices using lift-off of insulating film A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first i... | 03/20/2001 |
| 6117713 | Method of producing a MESFET semiconductor device having a recessed gate structure An insulating layer is formed on a semiconductor substrate, and a first resist layer having a first resist opening portion is formed on the insulating layer. Then, the insulating layer is etched thought the opening portion to expose the substrate. After r... | 09/12/2000 |
| 6051485 | Method of producing a platinum-metal pattern or structure by a lift-off process A method of producing a platinum-metal structure or pattern on a substrate, which includes the steps of applying a silicon oxide layer to the substrate; applying a mask to the silicon oxide layer which is formed with an opening at a location thereof at wh... | 04/18/2000 |
| 5981309 | Method for fabricating charge coupled device image sensor A method for fabricating a CCD image sensor includes the steps of forming a P type well in a surface of a semiconductor substrate, forming a buried CCD (BCCD) in a surface of the P type well, forming an offset gate and a reset gate on the BCCD at a predet... | 11/09/1999 |
| 5940697 | T-gate MESFET process using dielectric film lift-off technique An improved method for forming a T-gate structure in a MESFET includes dielectric lift-off steps.... | 08/17/1999 |
| 5882995 | Method of forming ohmic electrodes on semiconductor wafer In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in fir... | 03/16/1999 |
| 5869364 | Single layer integrated metal process for metal semiconductor field effect transistor (MESFET) A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etchi... | 02/09/1999 |
| 5858824 | Method of forming fine electrode on semiconductor substrate A dielectric film is formed on a semiconductor substrate, and on the dielectric film an inorganic dielectric mask film is deposited by CVD. The mask film comprises a first component which is relatively high in etch rate by isotropic plasma etching and a s... | 01/12/1999 |
| 5856232 | Method for fabricating T-shaped electrode and metal layer having low resistance A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing l... | 01/05/1999 |
| 5854086 | Method for manufacturing planar field effect transistors and planar high electron mobility transistors An apparatus and method of processing a planar HEMT or FET semiconductor device is disclosed. An ohmic metalization is patterned on a semiconductor surface then lifted-off. A plurality of process control monitors are isolated, preferably using a wet etch ... | 12/29/1998 |
| 5796132 | Semiconductor device On a semiconductor substrate with an active layer, a first-stage recess groove is formed by photolithography and wet or dry etching. On the semiconductor substrate and the surface of the first-stage recess groove, a surface passivation film a crystalline ... | 08/18/1998 |
| 5733806 | Method for forming a self-aligned semiconductor device A method for forming a self-aligned semiconductor device (10) having sidewall spacers (16,17) used to align the formation of a source region (23) and a drain region (24) along with the formation of a gate structure (35). Spacers (16,17) can be formed usin... | 03/31/1998 |
| 5705432 | Process for providing clean lift-off of sputtered thin film layers A unique photoresist process is provided which achieves clean and complete lift-off of a thin film layer such as a sputtered thin film formed on a photoresist which is formed above a semiconductor substrate. The process of the present invention relies on ... | 01/06/1998 |
| 5643807 | Method of manufacturing a semiconductor device comprising a buried channel field effect transistor A method of manufacturing a semiconductor device with a buried channel field effect transistor, comprising the formation of a stack of layers on a substrate with an active semiconductor layer having a non-zero aluminium (Al) content, a semiconductor cap l... | 07/01/1997 |
| 5610090 | Method of making a FET having a recessed gate structure A Field Effect Transistor having a recessed gate comprises a substrate, a source electrode and a drain electrode, a recessed channel region formed over an area of the semiconductor substrate between the source electrode and the drain electrode, and a gate... | 03/11/1997 |
| 5587328 | Method for manufacturing semiconductor device A semiconductor device manufacturing method with which a GaAs MESFET and an integrated circuit using the same can be manufactured cheaply and with high yield by accurately forming a mushroom-shaped gate electrode with inexpensive equipment and a short pro... | 12/24/1996 |
| 5563079 | Method of making a field effect transistor A method of making a FET includes the steps of forming a source and a drain at respective edges of the surface of a semiconductor substrate, forming a first insulation film on the whole surfaces of the semiconductor substrate, the source, and the drain, c... | 10/08/1996 |
| 5538910 | Method of making a narrow gate electrode for a field effect transistor A method of producing a field effect transistor that includes forming a step in a compound semiconductor substrate, forming a first insulating side wall at the step, forming an etch blocking layer on the substrate, removing the first insulating side wall,... | 07/23/1996 |
| 5486483 | Method of forming closely spaced metal electrodes in a semiconductor device A method of forming closely spaced metal electrodes contacting different regions of a semiconductor device is disclosed. The method includes first depositing a sacrificial layer over a developing semiconductor structure. Next, a photoresist layer is depos... | 01/23/1996 |
| 5432119 | High yield electron-beam gate fabrication method for sub-micron gate FETS Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material over-hanging the opening along both its elongate sides and its ends. A contact metal is next eva... | 07/11/1995 |
| 5385851 | Method of manufacturing HEMT device using novolak-based positive-type resist In a method of manufacturing a semiconductor apparatus, a resist is coated on a semiconductor substrate and baked. The resist is exposed with an electron beam, and an invertedly tapered opening is formed. Recess etching is performed on the semiconductor s... | 01/31/1995 |
| 5362677 | Method for producing a field effect transistor with a gate recess structure A field effect transistor has an active layer containing a multi-step recess that becomes narrower as it approaches the substrate. A gate electrode is produced at the deepest portion of the recess section. The transistor may be produced by successively se... | 11/08/1994 |
| 5338703 | Method for producing a recessed gate field effect transistor In a method for producing a recessed gate field effect transistor including a recess in a semiconductor substrate and a gate electrode disposed in the recess, a photoresist film is applied to the semiconductor substrate and source and drain electrodes on ... | 08/16/1994 |
