Class 438/564 - Polycrystalline semiconductor source

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes wherein the solid dopant source material is composed
No. of patents: 219
Last issue date: 09/02/2008

«First «Previous1 2 3 4 5 6 Next»Last»

Number	Title	Issue Date
7419872	Method for preparing a trench capacitor structure A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer su...	09/02/2008
7312125	Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and...	12/25/2007
7232484	Method and apparatus for doping semiconductors Semiconductor materials such as silicon particles are doped by mixing the semiconductor material with a solution having a dopan and a solvent. The solvent is removed from the wetted surface of the particles of the semiconductor material, thereby yielding particles t...	06/19/2007
7176109	Method for forming raised structures by controlled selective epitaxial growth of facet using spacer Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial laye...	02/13/2007
7141511	Method and apparatus for fabricating a memory device with a dielectric etch stop layer The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS ...	11/28/2006
7115465	Method for manufacturing a bipolar transistor A method for manufacturing a bipolar transistor, comprising the steps of: growing on the substrate a first semiconductor; depositing an encapsulation layer etchable with respect to the first semiconductor, forming a sacrificial blo...	10/03/2006
7045397	JFET and MESFET structures for low voltage high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th...	05/16/2006
6911384	Gate structure with independently tailored vertical doping profile A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second co...	06/28/2005
6905933	Method for forming raised structures by controlled selective epitaxial growth of facet using spacer Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial laye...	06/14/2005
6867113	In-situ deposition and doping process for polycrystalline silicon layers and the resulting device An in-situ deposition and doping method for polycrystalline silicon layers of semiconductor devices. A first intermediate layer of in-situ doped polycrystalline silicon is grown, and a second additional layer of polycrystalline silicon is grown with a lower doping l...	03/15/2005
6852603	Fabrication of abrupt ultra-shallow junctions One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the...	02/08/2005
6821870	Heterojunction bipolar transistor and method for fabricating the same A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be ...	11/23/2004
6808999	Method of making a bipolar transistor having a reduced base transit time A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening dispose...	10/26/2004
6797600	Method of forming a local interconnect A method of forming a local interconnect includes forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one o...	09/28/2004
6750091	Diode formation method A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the d...	06/15/2004
6677207	Vanishingly small integrated circuit diode An embodiment of the instant invention is a method of implementing a vanishingly small integrated circuit diode comprising the steps of: forming an area of a thin dielectric film (201 of FIG. 2) over a conductive silicon surface ( 10 of FIG. 2) of one con...	01/13/2004
6660571	High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re...	12/09/2003
6645795	Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain bou...	11/11/2003
6642134	Semiconductor processing employing a semiconductor spacer A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments ...	11/04/2003
6610587	Method of forming a local interconnect A method of forming a local interconnect includes forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain regi...	08/26/2003
6607957	Method for fabricating nitride read only memory The present invention relates to a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, defining the doped polysilicon layer by using a patterned mask layer to form a plurality of doped ...	08/19/2003
6569715	Large grain single crystal vertical thin film polysilicon mosfets A vertical thin film transistor formed in a single grain of polysilicon having few or no grain boundaries for use in memory, logic and display applications. The transistor is formed from a thin film of polysilicon having large columnar grains, in which so...	05/27/2003
6566208	Method to form elevated source/drain using poly spacer A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly do...	05/20/2003
6566212	Method of fabricating an integrated circuit with ultra-shallow source/drain extensions A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally ann...	05/20/2003
6506655	Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an...	01/14/2003
6498071	Manufacture of trench-gate semiconductor devices In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11') is provided in a trench (20) wi...	12/24/2002
6492282	Integrated circuits and manufacturing methods A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of ...	12/10/2002
6479352	Method of fabricating high voltage power MOSFET having low on-resistance Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of...	11/12/2002
6472287	Manufacturing method of semiconductor with a cleansing agent The present invention aims to suppress certainly the single-crystallizing in polycrystalline silicon that is to compose an emitter electrode, as well as to prevent the interface oxide film from remaining, when a heat treatment is conducted to diffuse dopa...	10/29/2002
6458693	Method of manufacturing a semiconductor device A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper...	10/01/2002
6406973	Transistor in a semiconductor device and method of manufacturing the same The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective ...	06/18/2002
6391752	Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier loweri...	05/21/2002
6391689	Method of forming a self-aligned thyristor A semiconductor substrate having a doped well region is provided. A gate stacking structure is formed on the doped well region. The gate stacking structure divides the doped well region into a first area and a second area. The second area is masked. The f...	05/21/2002
6372589	Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated circuit implant techniques. Damage is avoided by using solid...	04/16/2002
6372588	Method of making an IGFET using solid phase diffusion to dope the gate, source and drain A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating la...	04/16/2002
6365493	Method for antimony and boron doping of spherical semiconductors A method for doping crystals is disclosed. The method includes a receiver for receiving semiconductor spheres and doping powder. The semiconductor spheres and dopant powder are then directed to a chamber defined within an enclosure. The chamber maintains ...	04/02/2002
6329273	Solid-source doping for source/drain to eliminate implant damage A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped s...	12/11/2001
6309935	Methods of forming field effect transistors Methods of forming field effect transistors. In one aspect, a method of forming a field effect transistor includes: a) providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a d...	10/30/2001
6300210	Method of manufacturing a semiconductor device comprising a bipolar transistor The invention relates to the manufacture of a so-called double poly bipolar transistor. In a layer structure of a first insulating layer (4), a polycrystalline layer (5) of silicon and a second insulating layer (6), an opening (7) is formed which extends ...	10/09/2001
6294415	Method of fabricating a MOS transistor An improved method of fabricating a MOS transistor on a semiconductor wafer is disclosed. A pre-amorphization implant (PAI) process is used to dope the silicon substrate adjacent to the gate. The dopants formed in the silicon substrate during the first io...	09/25/2001

«First «Previous1 2 3 4 5 6 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 438/564 - Polycrystalline semiconductor source