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| Number | Title | Issue Date |
| 8053344 | Methods of forming integrated circuits A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is forme... | 11/08/2011 |
| 7915155 | Double trench for isolation of semiconductor devices Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a secon... | 03/29/2011 |
| 7651933 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is forme... | 01/26/2010 |
| 7419872 | Method for preparing a trench capacitor structure A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer su... | 09/02/2008 |
| 7393766 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polys... | 07/01/2008 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7223651 | Dram memory cell with a trench capacitor and method for production thereof A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substra... | 05/29/2007 |
| 7208382 | Semiconductor device with high conductivity region using shallow trench A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in... | 04/24/2007 |
| 7199006 | Planarization method of manufacturing a superjunction device A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivit... | 04/03/2007 |
| 7138331 | Method for manufacturing nano-gap electrode device Provided is a method for manufacturing a nano-gap electrode device comprising the steps of: forming a first electrode on a substrate; forming a spacer on a sidewall of the first electrode; forming a second electrode on an exposed substrate at a side of the spacer; a... | 11/21/2006 |
| 7118979 | Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, in... | 10/10/2006 |
| 7109100 | Semiconductor device and method for manufacturing semiconductor device To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer... | 09/19/2006 |
| 7078315 | Method for eliminating inverse narrow width effects in the fabrication of DRAM device The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (N... | 07/18/2006 |
| 7060598 | Method for implanting ions into semiconductor substrate An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plan... | 06/13/2006 |
| 7045397 | JFET and MESFET structures for low voltage high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th... | 05/16/2006 |
| 7033873 | Methods of controlling gate electrode doping, and systems for accomplishing same The present invention is generally directed to various methods of controlling gate electrode doping, and various systems for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises performing at least one process operation to form a... | 04/25/2006 |
| 7005364 | Method for manufacturing semiconductor device The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern. The method for manufacturing a semiconductor device in... | 02/28/2006 |
| 7005676 | Semiconductor device manufacturing method There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y≧0) and a peripheral region including an amorphous or polyc... | 02/28/2006 |
| 6995079 | Ion implantation method and method for manufacturing semiconductor device An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the ... | 02/07/2006 |
| 6982193 | Method of forming a super-junction semiconductor device In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor. ... | 01/03/2006 |
| 6924204 | Split gate flash memory cell and manufacturing method thereof A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is... | 08/02/2005 |
| 6919255 | Semiconductor trench structure A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of th... | 07/19/2005 |
| 6902982 | Trench capacitor and process for preventing parasitic leakage A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of ... | 06/07/2005 |
| 6762099 | Method for fabricating buried strap out-diffusions of vertical transistor A two-stage method for making buried strap out-diffusions is disclosed. A substrate having a deep trench is provided. A first conductive layer is deposited at the bottom of the deep trench. A collar oxide is formed on sidewalls of the deep trench. A second conductiv... | 07/13/2004 |
| 6750091 | Diode formation method A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the d... | 06/15/2004 |
| 6723580 | Method of forming a photodiode for an image sensor The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a ... | 04/20/2004 |
| 6695903 | Dopant pastes for the production of p, p+, and n, n+ regions in semiconductors The invention relates to novel boron, phosphorus or boron-aluminium dopant pastes for the production of p, p+ and n, n+ regions in monocrystalline and polycrystalline Si wafers, and of corresponding pastes for use as masking pastes in semiconductor fabric... | 02/24/2004 |
| 6660571 | High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re... | 12/09/2003 |
| 6645795 | Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain bou... | 11/11/2003 |
| 6579782 | Vertical power component manufacturing method A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant ... | 06/17/2003 |
| 6566201 | Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion A method for fabricating a high voltage power MOSFFT having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial laye... | 05/20/2003 |
| 6541347 | Method of providing planarity of a photoresist A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows i... | 04/01/2003 |
| 6531331 | Monolithic integration of a MOSFET with a MEMS device An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithi... | 03/11/2003 |
| 6528399 | MOSFET transistor with short channel effect compensated by the gate material A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in tha... | 03/04/2003 |
| 6458693 | Method of manufacturing a semiconductor device A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper... | 10/01/2002 |
| 6399436 | Method of making an electric conductive strip A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. N... | 06/04/2002 |
| 6346465 | Semiconductor device with silicide contact structure and fabrication method thereof A fabrication method of a semiconductor device that realizes a simplified contact formation process is provided. After a single-crystal silicon substrate having a main surface is provided, a dielectric film having a contact hole uncovering the main surfac... | 02/12/2002 |
| 6329274 | Method of producing semiconductor device For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activat... | 12/11/2001 |
| 6316310 | Method of forming a buried plate Known methods for forming trench storage capacitors require the chemical vapour deposition (CVD) of an undoped silicon oxide layer in order to prevent auto doping of side wall of a semiconductor trench. This layer is deposited once an arsenic doped silico... | 11/13/2001 |
| 6303436 | Method for fabricating a type of trench mask ROM cell A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the n... | 10/16/2001 |
