Class 438/556 - Edge diffusion by using edge portion of structure other than masking layer to mask

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes using an edge feature of the substrate other than
No. of patents: 39
Last issue date: 06/24/2008

Number	Title	Issue Date
7390678	Method for fabricating semiconductor device A PLZT film (30) is formed as the material film of a capacitor dielectric film and a top electrode film (31) is formed on the PLZT film (30). The top electrode film (31) comprises two IrOx films having different composition. Su...	06/24/2008
7232732	Semiconductor device with a toroidal-like junction Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is ...	06/19/2007
7169660	Lithography-independent fabrication of small openings for forming vertical mos transistor A method for formation of openings in semiconducting devices not limited by constraints of photolithography include forming a first dielectric layer over a semiconducting substrate, depositing a polysilicon layer over the first dielectric layer, forming a second die...	01/30/2007
7112531	Silicon oxide co-deposition/etching process Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon o...	09/26/2006
7045397	JFET and MESFET structures for low voltage high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th...	05/16/2006
6809016	Diffusion stop implants to suppress as punch-through in SiGe Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant ju...	10/26/2004
6780691	Method to fabricate elevated source/drain transistor with large area for silicidation A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the is...	08/24/2004
6582998	Method for fabricating nonvolatile semiconductor memory device Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, aft...	06/24/2003
6544811	Micromachined device having electrically isolated components and a method for making the same A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such ...	04/08/2003
6303410	Methods of forming power semiconductor devices having T-shaped gate electrodes Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the...	10/16/2001
6291328	Opto-electronic device with self-aligned ohmic contact layer An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact lay...	09/18/2001
6204110	Methods of forming an SRAM A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) ...	03/20/2001
6200872	Semiconductor substrate processing method A purchased silicon substrate 10 is subjected to D-HF treatment, SC-1 treatment, etc. to expose the surface of the silicon substrate 10. Then, the silicon substrate 10 having the surface exposed and containing grown-in defects 12 and micro oxygen precipit...	03/13/2001
5935649	Method for manufacturing SiOF films There is provided a method for reducing absorptivity of moisture of an insulation film made of SiOF and for achieving a highly reliable semiconductor device. In a method for manufacturing a semiconductor device utilizing a silicon oxide film including flu...	08/10/1999
5937289	Providing dual work function doping Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an a...	08/10/1999
5902135	Method for removing crystal defects in silicon wafers A method of removing vacancies in the crystal lattice of silicon wafers is provided. In particular, silicon wafers obtained from drawn rods have significantly higher defect densities in the central region as compared to the outer peripheries of the wafers...	05/11/1999
5786258	Method of making an SOI transistor A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by...	07/28/1998
5716879	Method of making a thin film transistor A structure and fabricating method of a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes: an insulation substrate; a gate electrode formed on the insulation substrate; a gate insulation film forme...	02/10/1998
5710053	Method for manufacturing thin film transistor for a liquid crystal display A method for manufacturing a thin-film transistor includes forming a silicon pattern on a substrate; forming a gate insulating film by a thermal oxidization process or a deposition process; forming a gate pattern by depositing a gate electrode and a gate ...	01/20/1998
5620912	Method of manufacturing a semiconductor device using a spacer A semiconductor device and manufacturing method wherein a gate insulating film is formed on a semiconductor substrate. A gate is formed on the gate insulating film and a sidewall spacer is formed on respective sides of the gate. The substrate is etched at...	04/15/1997
5605862	Process for making low-leakage contacts A semiconductor device having low-leakage borderless contacts is formed by etching contact openings adjacent first and second electronic elements of opposite dopant type, conformally depositing a thin doped polysilicon layer, protecting the electronic ele...	02/25/1997
5580797	Method of making SOI Transistor A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by...	12/03/1996
5308790	Selective sidewall diffusion process using doped SOG A selective sidewall diffusion process using doped SOG. A substrate is processed to form raised portions or pedestals, having sidewalls, and trenches. A first layer, either a doped SOG layer or undoped oxide layer, may be deposited onto the substrate adja...	05/03/1994
5079176	Method of forming a high voltage junction in a dielectrically isolated island A high voltage junction is formed in a dielectrically isolated island by forming a second conductivity type region in a first conductivity type island wherein the second conductivity type region extends to and between a pair of opposed dielectric isolatio...	01/07/1992
5066603	Method of manufacturing static induction transistors In fabricating a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is marked in a patt...	11/19/1991
5061656	Method for making a self-aligned impurity induced disordered structure A method for making a self-aligned IID structure for an LED (10) is provided. This self-aligned IID structure is accomplished by depositing a dopant layer (17) over the LED structure. A polymeric material is deposited over layer (17). The polymeric layer ...	10/29/1991
5028564	Edge doping processes for mesa structures in SOS and SOI devices Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage...	07/02/1991
5026663	Method of fabricating a structure having self-aligned diffused junctions A method of fabricating a semiconductor structure having self-aligned diffused junctions is provided wherein a first dielectric layer, a doped semiconductor layer and a second dielectric layer are formed on a semiconductor substrate. An opening extending ...	06/25/1991
4980315	Method of making a passivated P-N junction in mesa semiconductor structure A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentraton. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each h...	12/25/1990
4893166	High value semiconductor resistor In accordance with the teachings of this invention, resistors are fabricated in semiconductor devices utilizing a layer of semiconductor material having a preselected resistivity. Means are provided for electrically isolating the semiconductor region from...	01/09/1990
4833094	Method of making a dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant i...	05/23/1989
4743565	Lateral device structures using self-aligned fabrication techniques Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusi...	05/10/1988
4589190	Fabrication of drilled and diffused junction field-effect transistors A method for fabricating junction field-effect transistors includes forming in an N-type silicon substrate a plurality of high-aspect-ratio bores interposed between a source region and a drain region in the substrate, diffusing P-type impurities a predete...	05/20/1986
4435225	Method of forming self-aligned lateral bipolar transistor A lateral bipolar transistor having a base width of 0.5 micron or less is made by forming a protective layer on an electrically insulating layer along a surface of a semiconductor body, forming an open space through the protective layer so as to define a ...	03/06/1984
4380481	Method for fabricating semiconductor devices A method of fabricating a semiconductor device comprising forming an island-shaped multi-layered structure of oxides and nitrides on the surface of a semiconductor. The multi-layered structure is selectively etched to define diffusion windows for forming ...	04/19/1983
4210472	Manufacturing process of semiconductor devices Process of manufacturing semiconductor devices by providing on the surface of a substrate of one conductivity at first only a covering with a doping agent of the other conductivity and then, after the building of mesas, the PN-junction is formed by diffus...	07/01/1980
4038110	Planarization of integrated circuit surfaces through selective photoresist masking An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with t...	07/26/1977
4026740	Process for fabricating narrow polycrystalline silicon members A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region i...	05/31/1977
3954524	Self-aligning photoresist process for selectively opening tops of mesas in mesa-diode-array structures This disclosure relates to a self-aligned photoresist process for use in removing silicon dioxide from the tops of silicon mesas or other semiconductor mesa structures. The specific application is in the production of an array of mesa P-N diodes on a semi...	05/04/1976

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Class 438/556 - Edge diffusion by using edge portion of structure other than masking layer to mask