Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7407851 | DMOS device with sealed channel processing A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A fi... | 08/05/2008 |
| 7381635 | Method and structure for reduction of soft error rates in integrated circuits A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring l... | 06/03/2008 |
| 7354846 | Submount substrate for mounting light emitting device and method of fabricating the same A submount substrate for mounting a light emitting device and a method of fabricating the same, wherein since a submount substrate for mouthing a light emitting device in which a Zener diode device is integrated can be fabricated by means of a silicon bulk micromach... | 04/08/2008 |
| 7342269 | Photoelectric conversion device, and process for its fabrication In a photoelectric conversion device comprising a photoelectric-conversion section and a peripheral circuit section where signals sent from the photoelectric-conversion section are processed, the both sections being provided on the same semiconductor substrate, a se... | 03/11/2008 |
| 7192853 | Method of improving the breakdown voltage of a diffused semiconductor junction A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to defin... | 03/20/2007 |
| 7183126 | Method for forming an optical interfering pattern on a surface of a metal substrate, and article having an optical interfering effect An article having an optical interfering effect includes a metal substrate with a surface, and a pattern of micro-cavities formed on the surface of the metal substrate and exhibiting an optical interfering effect on the reflection of the pattern of the micro-cavitie... | 02/27/2007 |
| 7166232 | Method for producing a solid body including a microstructure According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated ... | 01/23/2007 |
| 7129169 | Method for controlling voiding and bridging in silicide formation A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile la... | 10/31/2006 |
| 7067383 | Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 06/27/2006 |
| 7008810 | Method for fabricating at least one mesa or ridge structure or at least one electrically pumped region in a layer or layer sequence A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for defi... | 03/07/2006 |
| 6905560 | Retarding agglomeration of Ni monosilicide using Ni alloys A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy l... | 06/14/2005 |
| 6893947 | Advanced RF enhancement-mode FETs with improved gate properties A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the st... | 05/17/2005 |
| 6825122 | Method for fabricating a patterned thin film and a micro device An organic resin with an optical crosslinking agent therein is coated to form an organic resin layer over a resist mast and a patterned thin film, and crosslinked. Although some debris are formed over the resist mask in the fabrication of the patterned thin film, th... | 11/30/2004 |
| 6780781 | Method for manufacturing an electronic device A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns u... | 08/24/2004 |
| 6605519 | Method for thin film lift-off processes using lateral extended etching masks and device A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotr... | 08/12/2003 |
| 6596556 | Light emitting diode and a method for manufacturing the same An LED is provided with a p-type semiconductor region in the shape of an island being buried in an n-type semiconductor region from the surface of it, and forms a pn junction at the interface between these n-type region and p-type region. The pn junction ... | 07/22/2003 |
| 6586303 | Method for fabricating a mask ROM A patterned photoresist layer is coated onto a semiconductor substrate. Then a doped region is formed in the semiconductor substrate not covered by the patterned photoresist layer. In addition, a semiconductor process is performed to trim the patterned ph... | 07/01/2003 |
| 6528398 | Thinning of trench and line or contact spacing by use of dual layer photoresist An exemplary embodiment described in the disclosure relates to a method of fabricating an integrated circuit which includes providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to... | 03/04/2003 |
| 6486048 | Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source + drain A method for fabricating semiconductor device capable of forming silicide suitable for highly integrated semiconductor device comprising the steps of: forming a conductive oxide layer and metal layer on a substrate having a gate and source/drain regions; ... | 11/26/2002 |
| 6444548 | Bitline diffusion with halo for improved array threshold voltage control A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusio... | 09/03/2002 |
| 6410388 | Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate wit... | 06/25/2002 |
| 6368921 | Manufacture of trench-gate semiconductor devices A trench-gate semiconductor device, for example a MOSFET or IGBT, of compact geometry is manufactured with self-aligned masking techniques in a simple process with good reproducibility. The source region (13) of the device is formed by introducing dopant ... | 04/09/2002 |
| 6303492 | Expanded implantation of contact holes A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-e... | 10/16/2001 |
| 6294445 | Single mask process for manufacture of fast recovery diode A single mask process for manufacture of a FRED employs a thick oxide layer over an N type silicon surface and a thin nitride layer over the oxide. A single mask defines FRED device spaced P diffusions. The oxide spanning the P diffusions is laterally etc... | 09/25/2001 |
| 6204110 | Methods of forming an SRAM A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) ... | 03/20/2001 |
| 6190979 | Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and... | 02/20/2001 |
| 6165870 | Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure An element isolation method, in particular, a shallow trench isolation (STI) method for semiconductor devices is disclosed in which a trench is formed to have a stepped structure shaped in such a fashion that it has a smaller width at its lower portion th... | 12/26/2000 |
| 6124167 | Method for forming an etch mask during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxi... | 09/26/2000 |
| 6100173 | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric re... | 08/08/2000 |
| 6071762 | Process to manufacture LDD TFT A process for manufacturing a TFT without the use of ion implantation is described. Instead, heavily doped layers of amorphous silicon are used as diffusion sources. Two embodiments of the invention are described. In the first embodiment the gate pedestal... | 06/06/2000 |
| 5998266 | Method of forming a semiconductor structure having laterally merged body layer A trenched gate MOSFET (metal oxide semiconductor field effect transistor) structure is fabricated via a novel process which includes the step of using a common mask serving the dual role as a mask for the body layer formation and as a mask for trench etc... | 12/07/1999 |
| 5891776 | Methods of forming insulated-gate semiconductor devices using self-aligned trench sidewall diffusion techniques A method of forming an insulated gate semiconductor device includes the steps of patterning an insulated gate electrode on a face of a substrate containing a first conductivity type region and forming a trench at the face using the gate electrode as a mas... | 04/06/1999 |
| 5856003 | Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particu... | 01/05/1999 |
| 5856228 | Manufacturing method for making bipolar device having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 01/05/1999 |
| 5700714 | Diffusion mask and fabrication method for forming pn-junction elements in a compound semiconductor substrate A pn-junction element is formed in a compound semiconductor substrate by depositing an aluminum-nitride film on the surface of the substrate, patterning the aluminum-nitride film to form a diffusion mask, depositing a diffusion source film on the diffusio... | 12/23/1997 |
| 5686322 | Process for doping two levels of a double poly bipolar transistor after formation of second poly layer A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher... | 11/11/1997 |
| 5641706 | Method for formation of a self-aligned N-well for isolated field emission devices A method for use in manufacture of field emitter devices is provided specifically for forming electron emitter tips in a doped semiconductor substrate. The method comprises the following steps: forming a depression around an emitter area in the substrate;... | 06/24/1997 |
| 5633186 | Process for fabricating a non-volatile memory cell in a semiconductor device A process for fabricating a non-volatile memory cell (10) in a semiconductor device includes the formation of a doped region (28) in a semiconductor substrate (40) underlying a floating gate electrode (16) and separated therefrom by a tunnel dielectric la... | 05/27/1997 |
| 5620907 | Method for making a heterojunction bipolar transistor A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystallin... | 04/15/1997 |
| 5618741 | Manufacture of electronic devices having thin-film transistors In the manufacture of a large-area electronic device (e.g. an active-matrix liquid-crystal display or other flat panel display), a TFT of improved lifetime stability results from the inclusion of a field-relief region (22) which is of lower doping concent... | 04/08/1997 |
