Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 7528058 | Method for producing a contact and electronic component comprising said type of contact The invention relates to a method for the production of passivated defining surfaces (6a, 6b) between a first layer, such as a silicide (5), and an adjacent layer. Passivating elements, such as S, Se and Te are used in said layer s... | 05/05/2009 |
| 7419872 | Method for preparing a trench capacitor structure A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer su... | 09/02/2008 |
| 6930007 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to ... | 08/16/2005 |
| 6887745 | Polysilicon thin film transistor and method of forming the same A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, ... | 05/03/2005 |
| 6849528 | Fabrication of ultra shallow junctions from a solid source with fluorine implantation One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the... | 02/01/2005 |
| 6844245 | Method of preparing a self-passivating Cu laser fuse A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a copper-alloy is deposited in the opening and the opening is filled with pure copper. The copper is planarize... | 01/18/2005 |
| 6809336 | Semiconductor device comprising sense amplifier and manufacturing method thereof A semiconductor device is provided which avoids lowering of the sense speeds of plural sense amplifiers due to their drives. In the semiconductor device, a P-type well layer (6) containing a P-type impurity is selectively disposed in a main surface of an epit... | 10/26/2004 |
| 6617209 | Method for making a semiconductor device having a high-k gate dielectric A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so th... | 09/09/2003 |
| 6436800 | Method for fabricating a non-volatile memory with a shallow junction A fabrication method for a nonvolatile memory with a shallow junction is described. A gate structure, comprising an electron-trapping layer and a conductive layer, is formed on a substrate. A doped spacer is formed on the sidewall of the gate structure. B... | 08/20/2002 |
| 6350645 | Strapping via for interconnecting integrated circuit structures A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a cont... | 02/26/2002 |
| 6255190 | Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants.... | 07/03/2001 |
| 6207540 | Method for manufacturing high performance MOSFET device with raised source and drain A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion... | 03/27/2001 |
| 6204110 | Methods of forming an SRAM A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) ... | 03/20/2001 |
| 5976940 | Method of making plurality of bipolar transistors In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substr... | 11/02/1999 |
| 5970343 | Fabrication of conductivity enhanced MOS-gated semiconductor devices In the manufacture of an MOS gated semiconductor device, indentations are provided on a surface of a semiconductor wafer extending inwardly of respective spaced apart regions at the wafer surface having doping concentrations greater than that present in t... | 10/19/1999 |
| 5789282 | Method for fabricating thin film transistor A method for fabricating a thin film transistor, comprising the steps of: forming a gate electrode; forming a doped polysilicon film for source/drain at the side wall of the gate electrode, to insulate the gate electrode; forming a gate insulating film; f... | 08/04/1998 |
| 5759887 | Semiconductor device and a method of manufacturing a semiconductor device A method of manufacturing a semiconductor integrated circuit (IC) includes the steps of forming a polycrystalline silicon layer containing impurities on a semiconductor substrate; forming an oxidation-resistant insulating layer on the polycrystalline sili... | 06/02/1998 |
| 5688714 | Method of fabricating a semiconductor device having a top layer and base layer joined by wafer bonding A method is set forth of manufacturing a silicon body (5) having an n-type top layer (1') and an adjoining, more highly doped n-type base layer (2'), by which a first, n-type silicon slice (1) and a second, more highly doped n-type silicon slice (2) are p... | 11/18/1997 |
| 5567644 | Method of making a resistor Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 10/22/1996 |
| 5529943 | Method of making buried bit line ROM with low bit line resistance A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. This reduces bit line sheet resistance a... | 06/25/1996 |
| 5491107 | Semiconductor processing method for providing large grain polysilicon films A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the ars... | 02/13/1996 |
| 5407857 | Method for producing a semiconductor device with a doped polysilicon layer by updiffusion There is provided a semiconductor device wherein a resistor layer is interposed between a semiconductor region and a surface electrode metal so as to improve a safe operation area of the device and enhance the secondary breakdown strength thereof, and a m... | 04/18/1995 |
| 5198370 | Method for producing an infrared detector In a method of producing an infrared detector, a first conductivity type semiconductor layer, in which lattice vacancies acting as first conductivity type carriers are formed by evaporation of an element during annealing, is formed on a substrate and dopa... | 03/30/1993 |
| 5185294 | Boron out-diffused surface strap process The invention provides a method for electrically connecting a polysilicon-filled trench to a diffusion region in a semiconductor device, wherein the trench and diffusion region are separated by a dielectric. The method provides for formation of a strap or... | 02/09/1993 |
| 5116784 | Method of forming semiconductor film Si2 H6 and PH3 are introduced into a heated reaction tube in which a plurality of substrates are contained under vacuum pressure, thereby forming phosphor-doped silicon films on the substrates. By changing the flow of Si | 05/26/1992 |
| 5098861 | Method of processing a semiconductor substrate including silicide bonding A method for processing at least two semiconductor wafers for producing a partially processed semiconductor substrate which can be subsequently further processed utilizing conventional planar semiconductor processing techniques to achieve a complementary ... | 03/24/1992 |
| 4977104 | Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon A method is provided for producing a semiconductor device characterized by filling hollows having a high aspect ratio with a semiconductor film doped with impurities as dopants and an undoped semiconductor film, given that the doped polycrystalline Si fil... | 12/11/1990 |
| 4960730 | Method of making a semiconductor light emitting device using out-diffusion from a buried stripe A buried stripe semiconductor light emitting device and a method for producing the device in which the buried stripe functions as an internal resonator, and the device has window regions interposed between the resonator and facets on the external surface ... | 10/02/1990 |
| 4904618 | Process for doping crystals of wide band gap semiconductors Non-equilibrium impurity incorporation is used to dope hard-to-dope crystals of wide band gap semiconductors, such as zinc selenide and zinc telluride. This involves incorporating into the crystal a compensating pair of primary and secondary dopants, ther... | 02/27/1990 |
| 4883769 | Method of making a multidimensional quantum-well array Multidimensional quantum-well arrays are made by electron-beam lithographic atterning, followed by solid-state diffusion.... | 11/28/1989 |
| 4833094 | Method of making a dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant i... | 05/23/1989 |
| 4761385 | Forming a trench capacitor A trench capacitor having increased capacitance. By means of the oxidation enhanced diffusion (OED) effect, locally outdiffused regions in the doped substrate of a semiconductor material may be formed. Thus, greater capacitance can be achieved for a trenc... | 08/02/1988 |
| 4734168 | Method of making n-silicon electrodes The photoelectrolysis of water by solar radiation to produce hydrogen and oxygen is achieved using semiconductor electrodes. The cell comprises a p-silicon wafer treated with catalyst as photocathode and metal doped n-silicon wafer as photoanode. The cell... | 03/29/1988 |
| 4605451 | Process for making thyristor devices A governing factor of the switching characteristics of a thyristor device is base layer resistivity, for example in a gate turn-off device, to maximize load current it is preferably low but, the reverse breakdown voltage of the emitter-base junction is im... | 08/12/1986 |
| 4588446 | Method for producing graded band gap mercury cadmium telluride The disclosure relates to a method for producing graded band gap mercury cadmium telluride, preferaby in narrow band gap mercury cadmium telluride, to reduce tunneling and the like by causing the surface region of the mercury cadmium telluride to lose mer... | 05/13/1986 |
| 4575466 | Treatment process for semiconductor wafer A process for preparing a semiconductor wafer having one region including impurities at a concentration of more than 5×1016 cm-3 therein, in which an energy beam is radiated onto this one region of the semiconductor wafer in order t... | 03/11/1986 |
| 4549914 | Integrated circuit contact technique A transfer layer is utilized to laterally redistribute impurities from a more heavily doped region to a lighter doped region. The contact to the source-drain region in advanced memory arrays has a width of the order of the minimum feature size. The source... | 10/29/1985 |
| 4475964 | Method of manufacturing a semiconductor device This invention provides a semiconductor device, which has a high impurity concentration diffusion region such as a drain diffusion region and a resistor comprising a polycrystalline silicon layer (which may be a load of a driver MOS transistor), and in wh... | 10/09/1984 |
| 4467518 | Process for fabrication of stacked, complementary MOS field effect transistor circuits A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five termina... | 08/28/1984 |
| 4329772 | Method for manufacturing a semiconductor device utilizing selective epitaxial growth and post heat treating Disclosed is an improved method of growing an epitaxial layer preventing auto-doping from a doped region exposed to a surface of a semiconductor substrate. A surface of a semiconductor substrate of one conductivity type is covered with a mask having a pre... | 05/18/1982 |
