Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 8110488 | Method for increasing etch rate during deep silicon dry etch A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to anothe... | 02/07/2012 |
| 7700469 | Methods of forming semiconductor constructions Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and a... | 04/20/2010 |
| 7687385 | Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface porti... | 03/30/2010 |
| 7544592 | Method for increasing etch rate during deep silicon dry etch A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to anothe... | 06/09/2009 |
| 7396757 | Interconnect structure with dielectric air gaps An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a ... | 07/08/2008 |
| 7393794 | Pattern formation method After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to f... | 07/01/2008 |
| RE40275 | Method for producing a memory cell A method for producing a memory cell includes masking a desired polysilicon structure with an oxidation-inhibiting layer, preferably a nitride layer. The polysilicon above source/drain regions and field regions is then converted into silicon dioxide. At the same tim... | 04/29/2008 |
| 7348279 | Method of making an integrated circuit, including forming a contact In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mas... | 03/25/2008 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ... | 12/04/2007 |
| 7262127 | Method for Cu metallization of highly reliable dual damascene structures The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectr... | 08/28/2007 |
| 7098142 | Method of etching ferroelectric devices A method of etching a ferroelectric device 100 having a ferroelectric layer 112 between a top and a bottom electrode 114, 108 is disclosed herein. Hardmasks 116, 118 are deposited on the top electrode 114, two or more hardmasks bei... | 08/29/2006 |
| 7022466 | Pattern formation method Pattern exposure is performed by selectively irradiating a resist film with extreme UV of a wavelength of a 1 nm through 30 nm band at exposure energy of 5 mJ/cm2 or less. After the pattern exposure, the resist film is developed so as to form a resist pat... | 04/04/2006 |
| 6955726 | Mask and mask frame assembly for evaporation A mask frame assembly includes a frame having an opening and a mask having at least two unit mask elements. Both ends of each unit mask element are fixed to the frame in a state of tension. The unit mask elements include a unit masking pattern, and overlap each othe... | 10/18/2005 |
| 6893987 | Simple process for fabricating semiconductor devices An alignment pattern is required for photo masks to be exactly aligned with one another; an amorphous silicon is deposited over the entire surface of an insulating layer except for an area where the alignment pattern is to be formed, and a pattern for an ion-implant... | 05/17/2005 |
| 6878577 | Method of forming LDD of semiconductor devices A method of forming an LDD of a semiconductor device. A substrate having a polysilicon layer thereon is provided, wherein the polysilicon layer comprises a first region and a second region. A patterned photoresist layer is formed on the polysilicon layer for exposin... | 04/12/2005 |
| 6797578 | Method for fabrication of emitter of a transistor and related structure A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undo... | 09/28/2004 |
| 6780781 | Method for manufacturing an electronic device A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns u... | 08/24/2004 |
| 6716730 | Pattern formation method After pre-baking a resist film, a solvent included in the resist film is vaporized. After vaporizing the solvent included in the resist film, pattern exposure is performed by selectively irradiating the resist film with exposing light in vacuum. The resist film is d... | 04/06/2004 |
| 6703266 | Method for fabricating thin film transistor array and driving circuit A method for fabricating a thin film transistor array and driving circuit comprising the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form ... | 03/09/2004 |
| 6613655 | Method of fabricating system on chip device A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device r... | 09/02/2003 |
| 6573167 | Using a carbon film as an etch hardmask for hard-to-etch materials A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO2, RuO2, BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sput... | 06/03/2003 |
| 6548385 | Method for reducing pitch between conductive features, and structure formed using the method A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the cond... | 04/15/2003 |
| 6306709 | Semiconductor device and manufacturing method thereof In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. Th... | 10/23/2001 |
| 6248650 | Self-aligned BJT emitter contact A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the e... | 06/19/2001 |
| 6136656 | Method to create a depleted poly MOSFET A structure and method for forming a semiconductor structure includes forming a plurality of device layers on a substrate (the device layers including a blocking layer having a thickness correlating to a magnitude of implant attenuation), removing the blo... | 10/24/2000 |
| 6096591 | Method of making an IGFET and a protected resistor with reduced processing steps A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating... | 08/01/2000 |
| 6060330 | Method of customizing integrated circuits by selective secondary deposition of interconnect material A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with a standard precision mask to define all possible connections, vias or cut-points, and 2) using a targeting energy beam to select the de... | 05/09/2000 |
| 5904552 | Method of resistless patterning of a substrate for implantation A method of ion implanting a substrate is disclosed, which includes providing a substrate having a surface. A sacrificial layer of semiconductor material is formed on the surface and resistlessly patterning to define masked and unmasked portions. The unma... | 05/18/1999 |
| 5753548 | Method for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETS A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion i... | 05/19/1998 |
| 5723354 | Solid state image pickup device and manufacturing method therefor A method for manufacturing a light receiving portion for a solid state image pickup device includes the steps of forming a well of a second impurity type on a substrate of a first impurity type, forming a channel stop within an upper surface of the well, ... | 03/03/1998 |
| 5686322 | Process for doping two levels of a double poly bipolar transistor after formation of second poly layer A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher... | 11/11/1997 |
| 5679586 | Composite mask process for semiconductor fabrication This is a method of making a semiconductor device comprising covering a first semiconductor compound having a plurality of windows on a major surface of a semiconductor body, covering a second semiconductor compound on selected windows of the first compou... | 10/21/1997 |
| 5198370 | Method for producing an infrared detector In a method of producing an infrared detector, a first conductivity type semiconductor layer, in which lattice vacancies acting as first conductivity type carriers are formed by evaporation of an element during annealing, is formed on a substrate and dopa... | 03/30/1993 |
| 4927772 | Method of making high breakdown voltage semiconductor device A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower co... | 05/22/1990 |
| 4837176 | Integrated circuit structures having polycrystalline electrode contacts and process A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithograp... | 06/06/1989 |
| 4692998 | Process for fabricating semiconductor components A process for the fabrication of semiconductor components and in particular a process in which the components are fabricated with a controlled spacing of etched channels. The process is in particular utilized in fabricating a monolithic array of elements ... | 09/15/1987 |
| 4586243 | Method for more uniformly spacing features in a semiconductor monolithic integrated circuit The unique initial masking step is used in a method of more predictably and uniformly spacing features on a surface of a semiconductor device by combinining it with two dielectric maskants. A unique semiconductor device masking is claimed in which semicon... | 05/06/1986 |
| 4517728 | Manufacturing method for MIS-type semiconductor device A manufacturing method for an MIS type semiconductor device features in the preferred form a single masking operation used to define source, gate, and drain windows simultaneously in an upper insulating oxide layer disposed over a semiconducting polysilic... | 05/21/1985 |
| 4443932 | Self-aligned oxide isolated process and device Improved self-aligned semiconductor devices are made using two sets of superposed pattern forming layers; a master mask layer set containing the self-aligned patterns, and a pattern selector layer set which allows different apertures in the master mask la... | 04/24/1984 |
| 4400867 | High conductivity metallization for semiconductor integrated circuits A method for simultaneously patterning-over field oxide, gate oxide, and sidewall oxide--high conductivity metal-silicide electrode metallization for semiconductor integrated circuits involves (1) formation of an unpatterned polycrystalline silicon (polys... | 08/30/1983 |
