Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 8105929 | Gate control and endcap improvement A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode la... | 01/31/2012 |
| 7972949 | Electronic component and display device and a method of manufacturing the same An electronic component or display device of the present invention can be provided by using a following pattern formation method. On a substrate treated with a first etching with a first resist pattern as a first mask, a second resist pattern is transfer-printed on ... | 07/05/2011 |
| 7943498 | Method of forming micro pattern in semiconductor device A method of forming a micro pattern in a semiconductor device includes: forming an target layer, a hard mask layer and first sacrificial patterns over a semiconductor substrate on which a cell gate region, a selective transistor region and a periphery circuit region... | 05/17/2011 |
| 7829447 | Semiconductor structure pattern formation Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. T... | 11/09/2010 |
| 7754591 | Method for forming fine pattern of semiconductor device A method for forming a fine pattern of a semiconductor device include forming a stack structure including a 1st layer hard mask film to a nth layer hard mask film (n is an integer ranging from 2 or more) over an underlying layer formed over a s... | 07/13/2010 |
| 7432179 | Controlling gate formation by removing dummy gate structures A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode la... | 10/07/2008 |
| 7407851 | DMOS device with sealed channel processing A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A fi... | 08/05/2008 |
| 7396757 | Interconnect structure with dielectric air gaps An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a ... | 07/08/2008 |
| 7348198 | Liquid crystal display device and fabricating method thereof A liquid crystal display device and a fabricating method thereof for simplifying a process and improving an aperture ratio are disclosed, including forming a first mask pattern group including a gate line, a gate electrode and a common line; forming a second mask pa... | 03/25/2008 |
| 7330709 | Receiver circuit using nanotube-based switches and logic Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. ... | 02/12/2008 |
| 7329606 | Semiconductor device having nanowire contact structures and method for its fabrication A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a dop... | 02/12/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7318993 | Resistless lithography method for fabricating fine structures A resistless lithography method for fabricating fine stiuctures is disclosed. IN an embodiment, a semiconductor mask layer (HM) may be formed on a carrier material (TM, HM′) and a selective ion implantation (I) being effected in order to dope selected regions (... | 01/15/2008 |
| 7262127 | Method for Cu metallization of highly reliable dual damascene structures The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectr... | 08/28/2007 |
| 7259107 | Method of forming isolated features of semiconductor devices A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an a... | 08/21/2007 |
| 7247536 | Vertical DRAM device with self-aligned upper trench shaping A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, ... | 07/24/2007 |
| 7245068 | Apparatus for controlled alignment of catalytically grown nanostructures Systems and methods are described for controlled alignment of catalyticaly grown nanostructures in a large-scale synthesis process. An apparatus includes an electrode including: a protruding section defining an edge; and a nonprotruding section coupled to the protru... | 07/17/2007 |
| 7241688 | Aperture masks for circuit fabrication Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circui... | 07/10/2007 |
| 7238543 | Methods for marking a bare semiconductor die including applying a tape having energy-markable properties A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cros... | 07/03/2007 |
| 7239076 | Self-aligned gated rod field emission device and associated method of fabrication A self-aligned gated field emission device and an associated method of fabrication are described. The device includes a substrate and a porous layer disposed adjacent to the surface of the substrate, wherein the porous layer defines a plurality of substantially cyli... | 07/03/2007 |
| 7196343 | Optical element, lithographic apparatus including such an optical element, device manufacturing method, and device manufactured thereby An optical element including an anti-reflection (AR) coating is configured to reflect Extreme-Ultra-Violet (EUV) radiation only. ... | 03/27/2007 |
| 7196012 | Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency incl... | 03/27/2007 |
| 7182812 | Direct synthesis of oxide nanostructures of low-melting metals The bulk synthesis of highly crystalline noncatalytic low melting metals such as β-gallium oxide tubes, nanowires, and nanopaintbrushes is accomplished using molten gallium and microwave plasma containing a mixture of monoatomic oxygen and hydrogen. Gallium oxide n... | 02/27/2007 |
| 7183205 | Method of pitch dimension shrinkage Roughly described, a patterned first layer is provided over a second layer which is formed over a substrate. In a conversion process, first layer material is consumed at feature sidewalls to form third layer material at the feature sidewalls. The width of third laye... | 02/27/2007 |
| 7169685 | Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped a... | 01/30/2007 |
| 7153780 | Method and apparatus for self-aligned MOS patterning A method of forming a thin film stack on a substrate, wherein the thin film stack includes at least a polysilicon layer and an oxide layer; forming a hardmask layer on the thin film stack; forming an anti-reflective coating (ARC) layer on the hardmask layer; pattern... | 12/26/2006 |
| 7125775 | Method for forming hybrid device gates A method for forming self-aligned contact devices in a core region of a semiconductor substrate and non-self-aligned contact devices in a non-core region of the semiconductor substrate is disclosed in which a single gate film stack is used for forming gate structure... | 10/24/2006 |
| 7109500 | Mask pattern correction method, semiconductor device manufacturing method, mask manufacturing method and mask A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high acc... | 09/19/2006 |
| 7106124 | Field emission RF amplifier A field emission RF amplifier. The field emission RF amplifier includes one or more RF amplification units on a substrate and held in a vacuum state and facing a reflection electrode. The RF amplification unit includes a cathode electrode, gate electrode, and an ano... | 09/12/2006 |
| 7098121 | Method of forming a film of predetermined pattern on a surface as well as device manufactured by employing the same, and method of manufacturing device An object is to provide a mask formation method, which can curtail a manufacturing cost. A method of forming a film of predetermined pattern on the front surface of a member to-be-processed is so constructed as to carry out the step (S178) of improving... | 08/29/2006 |
| 7094612 | Method of controlling a potential difference between a stencil mask and a substrate of semiconductor device A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through ... | 08/22/2006 |
| 7094618 | Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The pr... | 08/22/2006 |
| 7064846 | Non-lithographic shrink techniques for improving line edge roughness and using imperfect (but simpler) BARCs The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) and/or standing wave expression during pattern line formation in an integr... | 06/20/2006 |
| 7060996 | Mask, method of producing mask, and method of producing semiconductor device To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a sem... | 06/13/2006 |
| 6979616 | Method for fabricating semiconductor device with dual gate dielectric structure Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for th... | 12/27/2005 |
| 6976897 | Field emission array with carbon nanotubes and method for fabricating the field emission array A field emission array adopting carbon nanotubes as an electron emitter source, wherein the array includes a rear substrate assembly including cathodes formed as stripes over a rear substrate and carbon nanotubes; a front substrate assembly including anodes formed a... | 12/20/2005 |
| 6972253 | Method for forming dielectric barrier layer in damascene structure A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing ... | 12/06/2005 |
| 6962825 | Exposure apparatus Disclosed is an exposure apparatus for printing, by exposure, a pattern of an original on a substrate, which includes a housing tightly filled with a predetermined ambience and for accommodating therein at least a portion of an exposure light optical axis, and a det... | 11/08/2005 |
| 6955726 | Mask and mask frame assembly for evaporation A mask frame assembly includes a frame having an opening and a mask having at least two unit mask elements. Both ends of each unit mask element are fixed to the frame in a state of tension. The unit mask elements include a unit masking pattern, and overlap each othe... | 10/18/2005 |
| 6946339 | Method for creating a stepped structure on a substrate In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide laye... | 09/20/2005 |
