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| Number | Title | Issue Date |
| 8178432 | Semiconductor device and method for fabricating the same Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall s... | 05/15/2012 |
| 7790589 | Method of providing enhanced breakdown by diluted doping profiles in high-voltage transistors A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described. ... | 09/07/2010 |
| 7579264 | Method for manufacturing an electrode structure of a MOS semiconductor device A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a semiconductor substrate, forming a laminated body on the first insulating film that includes a polysilicon film and a metal film that is separated from the... | 08/25/2009 |
| 7456086 | Semiconductor having structure with openings A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pr... | 11/25/2008 |
| 7435669 | Method of fabricating transistor in semiconductor device A method of fabricating a transistor in a semiconductor device. A gate oxide layer and a gate are formed on a semiconductor substrate. An oxide layer and a silicon nitride layer are stacked on the substrate. The stacked oxide and silicon nitride layers are etched ba... | 10/14/2008 |
| 7358167 | Implantation process in semiconductor fabrication A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a ... | 04/15/2008 |
| 7312137 | Transistor with shallow germanium implantation region in channel A transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the w... | 12/25/2007 |
| 7297579 | Semiconductor device and manufacturing method thereof The objectives of the present invention are achieving TFTs having a small off current and TFT structures optimal for the driving conditions of a pixel portion and driver circuits, and providing a technique of making the differently structured TFTs without increasing... | 11/20/2007 |
| 7285833 | Selective doping and thermal annealing method for forming a gate electrode pair with different work functions A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material ha... | 10/23/2007 |
| 7282417 | Ion doping method to form source and drain An ion doping method to form source and drain is disclosed. First form a gate structure and a gate spacer on a semiconductor substrate, and then use dielectric layer having trenches therein to define heavily ion-doped positions and use a Y-shaped polysilicon layer f... | 10/16/2007 |
| 7208397 | Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the sourc... | 04/24/2007 |
| 7199031 | Semiconductor system having a pn transition and method for manufacturing a semiconductor system A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivi... | 04/03/2007 |
| 7198992 | Method of manufacturing a semiconductor device comprising doping steps using gate electrodes and resists as masks The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semicon... | 04/03/2007 |
| 7148534 | Angled implant in a fabrication technique to improve conductivity of a base material Ion implantation may be used to break up a dielectric layer that forms during the fabrication of a memory array. More specifically, during the fabrication of wordline stacks, a nitride layer may form between the polysilicon layer and the conductive metal layers abov... | 12/12/2006 |
| 7144797 | Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at ... | 12/05/2006 |
| 7141840 | Semiconductor device and production method therefor A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the sili... | 11/28/2006 |
| 7026230 | Method for fabricating a memory device The present invention is a method for fabricating a memory device. In one embodiment, an impurity concentration is created in a semiconductor substrate of a memory device. An annealing process is then performed. A second impurity concentration is created in a second... | 04/11/2006 |
| 7015562 | High-voltage diode A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 ... | 03/21/2006 |
| 7008865 | Method of manufacturing a semiconductor device having a high breakdown voltage and low on-resistance A semiconductor device includes a semiconductor substrate of a first conductivity type, in which an extended drain region of a second conductivity type and a source region of the second conductivity type are formed with an interval therebetween, wherein the extended... | 03/07/2006 |
| 6979646 | Hardening of copper to improve copper CMP performance A method for reducing the topography from CMP of metal layers during the semiconductor manufacturing process is described. Small amounts of solute are introduced into the conductive metal layer before polishing, resulting in a material with electrical conductivity a... | 12/27/2005 |
| 6933188 | Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape... | 08/23/2005 |
| 6927153 | Ion implantation with multiple concentration levels A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dim... | 08/09/2005 |
| 6888211 | High-voltage diode A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 ... | 05/03/2005 |
| 6858520 | Method of manufacturing semiconductor device A MOS semiconductor device is manufactured by providing a gate electrode on a semiconductor substrate through a silicon oxide film and disposing a resist mask pattern in contact with the silicon oxide film. The resist mask pattern has a fully opened region and a par... | 02/22/2005 |
| 6852610 | Semiconductor device and method for manufacturing the same A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation ... | 02/08/2005 |
| 6825104 | Semiconductor device with selectively diffused regions The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first majo... | 11/30/2004 |
| 6803298 | Method of manufacturing a device with epitaxial base A high voltage electrical device (20), having a substrate layer (22), base layer (24) and top layer (26), provides high voltage properties in excess of 1000V. Slicing a wafer (28) from an ingot (30) created in by monocrystal... | 10/12/2004 |
| 6800514 | Method of fabricating a MOS transistor with a drain extension and corresponding transistor A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first side... | 10/05/2004 |
| 6780685 | Semiconductor device and manufacturing method thereof A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and... | 08/24/2004 |
| 6756290 | Method for the production of a semiconductor device A method for making a semiconductor device having a pattern of highly doped regions located some distance apart in a semiconductor substrate and regions of low doping located between the highly doped regions. A diffusion barrier material is applied to the semiconduc... | 06/29/2004 |
| 6756272 | Method of manufacturing non-volatile semiconductor memory device Memory cells 10, according to the present invention, are comprised of a semiconductor substrate 2, and device isolating/insulating films 3 on the semiconductor substrate 2. A source region 4 and drain regions 5 are formed on... | 06/29/2004 |
| 6730584 | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate ... | 05/04/2004 |
| 6716714 | Semiconductor diode and method for producing the same A semiconductor arrangement and a method for manufacturing the semiconductor arrangement are provided, which arrangement and method allow an improvement in the current-carrying capacity for given chip dimensions. The semiconductor arrangement includes trenches intro... | 04/06/2004 |
| 6716712 | Process for producing two differently doped adjacent regions in an integrated semiconductor During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first regi... | 04/06/2004 |
| 6709961 | Method for fabricating semiconductor device As impurity ions for forming a channel, heavy ions are implanted multiple times at a dose such that no dislocation-loop defect layer is caused to be formed, and an annealing process is performed after each ion implantation process has been carried out, thereby formi... | 03/23/2004 |
| 6693014 | Method of improving static refresh A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffus... | 02/17/2004 |
| 6680225 | Method for manufacturing a semiconductor memory The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the po... | 01/20/2004 |
| 6673688 | Method for eliminating collector-base band gap in an HBT According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between a first depth and a second depth in the base. According to this exempla... | 01/06/2004 |
| 6642122 | Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz... | 11/04/2003 |
| 6639272 | Charge compensation semiconductor configuration Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric field can be chosen to have approximately the same magnitude in all of the compensation region... | 10/28/2003 |
