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| Number | Title | Issue Date |
| 7964485 | Method of forming a region of graded doping concentration in a semiconductor device and related apparatus A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to cr... | 06/21/2011 |
| 7951696 | Methods for simultaneously forming N-type and P-type doped regions using non-contact printing processes Methods for simultaneously forming doped regions of opposite conductivity using non-contact printing processes are provided. In one exemplary embodiment, a method comprises the steps of depositing a first liquid dopant comprising first conductivity-determining type ... | 05/31/2011 |
| 7670937 | Method for producing doped regions in a substrate, and photovoltaic cell Method for producing doped regions on the rear face of a photovoltaic cell. A doping paste with a first type of conductivity is deposited on a rear face of a semiconductor-based substrate according to a pattern consistent with the desired distribution of regions dop... | 03/02/2010 |
| 7407875 | Low resistance contact structure and fabrication thereof Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of ... | 08/05/2008 |
| 7384825 | Methods of fabricating phase change memory elements having a confined portion of phase change material on a recessed contact Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall compri... | 06/10/2008 |
| 7371648 | Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a... | 05/13/2008 |
| 7338876 | Method for manufacturing a semiconductor device A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor subs... | 03/04/2008 |
| 7247578 | Method of varying etch selectivities of a film A method of patterning a crystalline film. A crystalline film having a degenerate lattice comprising first atoms in a first region and a second region is provided. Dopants are substituted for said first atoms in said first region to form a non-degenerate crystalline... | 07/24/2007 |
| 7235436 | Method for doping structures in FinFET devices A method for doping fin structures in FinFET devices includes forming a first glass layer on the fin structure of a first area and a second area. The method further includes removing the first glass layer from the second area, forming a second glass layer on the fin... | 06/26/2007 |
| 7226803 | Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concent... | 06/05/2007 |
| 7144751 | Back-contact solar cells and methods for fabrication Methods for fabrication of emitter wrap through (EWT) back-contact solar cells and cells made by such methods. Certain methods provide for higher concentration of dopant in conductive vias compared to the average dopant concentration on front or rear surfaces, and p... | 12/05/2006 |
| 7115437 | Micromachined device having electrically isolated components and a method for making the same A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the do... | 10/03/2006 |
| 7109098 | Semiconductor junction formation process including low temperature plasma deposition of an optical absorption layer and high speed optical annealing A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the w... | 09/19/2006 |
| 7045449 | Methods of forming semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 05/16/2006 |
| 7005364 | Method for manufacturing semiconductor device The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern. The method for manufacturing a semiconductor device in... | 02/28/2006 |
| 6900113 | Method for producing bonded wafer and bonded wafer The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer)... | 05/31/2005 |
| 6897103 | MOS integrated circuit with reduced on resistance An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The islan... | 05/24/2005 |
| 6887745 | Polysilicon thin film transistor and method of forming the same A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, ... | 05/03/2005 |
| 6852563 | Process of fabricating electro-optic polymer devices with polymer sustained microelectrodes A process for fabricating an electro-optic device is decribed that includes: a) providing a substrate comprising at least two polymer micro-ridges, where each polymer micro-ridge comprises an upper surface and two walls, and the two walls form an angle with a lower ... | 02/08/2005 |
| 6797597 | Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of region... | 09/28/2004 |
| 6706606 | Buried zener diode structure and method of manufacture A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface. ... | 03/16/2004 |
| 6645820 | Polycrystalline silicon diode string for ESD protection of different power supply connections An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit... | 11/11/2003 |
| 6613974 | Tandem Si-Ge solar cell with improved conversion efficiency P-type and n-type regions are defined in the first surface of a substrate upon which is formed an epitaxial layer of preferably Si--Ge material, preferably capped by Si material. During epitaxy formation, dopant in the defined regions diffuses down to for... | 09/02/2003 |
| 6468825 | Method for producing semiconductor temperature sensor A method for producing a semiconductor temperature sensor comprises the steps of forming PNP bipolar transistors and PMOS transistors so that a base region of each of the PNP bipolar transistors and a corresponding N-well region of each of the PMOS transi... | 10/22/2002 |
| 6342418 | Semiconductor device and manufacturing method thereof An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a s... | 01/29/2002 |
| 6329251 | Microelectronic fabrication method employing self-aligned selectively deposited silicon layer Within a method for fabricating a microelectronic device there is first provided a silicon substrate. There is then formed upon the silicon substrate a first series of structures having a comparatively narrow spacing which leaves exposed a first series of... | 12/11/2001 |
| 6303436 | Method for fabricating a type of trench mask ROM cell A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the n... | 10/16/2001 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6177298 | Electrostatic discharge protection circuit for an integrated circuit and method of manufacturing An ESD protection circuit (11) includes a low capacitance diode (26), a voltage divider, a trigger transistor (16), and an SCR. Reducing the capacitance associated with the diode (26) makes the ESD protection circuit particularly suitable for RF applicati... | 01/23/2001 |
| 6162711 | In-situ boron doped polysilicon with dual layer and dual grain structure for use in integrated circuits manufacturing A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an origin... | 12/19/2000 |
| 6156594 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, ope... | 12/05/2000 |
| 6117719 | Oxide spacers as solid sources for gallium dopant introduction Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on t... | 09/12/2000 |
| 6110276 | Method for making n-type semiconductor diamond A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond ... | 08/29/2000 |
| 6103561 | Depletion mode MOS capacitor with patterned VT implants A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of... | 08/15/2000 |
| 6051488 | Methods of forming semiconductor switching devices having trench-gate electrodes Methods of forming semiconductor switching devices having trench-gate electrodes include the steps of implanting base region dopants of second conductivity type into a semiconductor substrate to define a preliminary base region therein. A step is then per... | 04/18/2000 |
| 5933721 | Method for fabricating differential threshold voltage transistor pair A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differenti... | 08/03/1999 |
| 5930616 | Methods of forming a field effect transistor and method of forming CMOS circuitry A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickne... | 07/27/1999 |
| 5913116 | Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a subst... | 06/15/1999 |
| 5909616 | Method of forming CMOS circuitry A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickne... | 06/01/1999 |
| 5908305 | Electro-optic device The device comprises a layer of silicon separated from a substrate by a layer of insulating material. A rib having an upper surface and two side surfaces is formed in the layer of silicon to provide a waveguide for the transmission of optical signals. A l... | 06/01/1999 |
