Class 438/547 - Simultaneously

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes wherein the multiple electrically active impurities
No. of patents: 53
Last issue date: 12/05/2006

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Number	Title	Issue Date
7144795	Method for forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the...	12/05/2006
7005364	Method for manufacturing semiconductor device The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern. The method for manufacturing a semiconductor device in...	02/28/2006
6988900	Surface mount connector assembly A surface mount connector assembly for mounting to a printed wiring board (PWB) in a low-profile manner. The height of the surface mount connector assembly is diminished because the connector assembly extends from one side of the PWB to the other through an opening ...	01/24/2006
6977204	Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do...	12/20/2005
6927137	Forming a retrograde well in a transistor to enhance performance of the transistor A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A fir...	08/09/2005
6912151	Negative differential resistance (NDR) based memory device with reduced body effects A memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs. Various embodiments...	06/28/2005
6825104	Semiconductor device with selectively diffused regions The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first majo...	11/30/2004
6713351	Double diffused field effect transistor having reduced on-resistance A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of t...	03/30/2004
6551903	Melt through contact formation method A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a ...	04/22/2003
6537899	Semiconductor device and a method of fabricating the same The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film 3, a gate insul...	03/25/2003
6448161	Silicon based vertical tunneling memory cell A method of forming a memory device from a single transistor and a single RTD structure is provided. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon ...	09/10/2002
6410410	Method of forming lightly doped regions in a semiconductor device A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped so...	06/25/2002
6342418	Semiconductor device and manufacturing method thereof An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a s...	01/29/2002
6303410	Methods of forming power semiconductor devices having T-shaped gate electrodes Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the...	10/16/2001
6297119	Semiconductor device and its manufacture The present invention discloses a semiconductor device having a PNP bipolar transistor and an NPN bipolar transistor having excellent transistor characteristics formed on the same semiconductor substrate, and a method of manufacturing the semiconductor de...	10/02/2001
6162711	In-situ boron doped polysilicon with dual layer and dual grain structure for use in integrated circuits manufacturing A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an origin...	12/19/2000
6153516	Method of fabricating a modified polysilicon plug structure A process for forming a modified polysilicon plug structure, used to connect a bit line structure, of a semiconductor memory device, to an underlying source and drain region, of a transfer gate transistor, has been developed. The process features the form...	11/28/2000
6110276	Method for making n-type semiconductor diamond A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond ...	08/29/2000
6080614	Method of making a MOS-gated semiconductor device with a single diffusion A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffus...	06/27/2000
5710059	Method for producing a semiconductor device having a semiconductor layer of SiC by implanting A method for producing a semiconductor device comprises a step of implanting first conductivity type impurity dopants of at least two different elements in a semiconductor layer being doped according to a second opposite conductivity type, and after that ...	01/20/1998
5670394	Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a pa...	09/23/1997
5650347	Method of manufacturing a lightly doped drain MOS transistor A method of manufacturing a lightly doped drain MOS transistor having the double shallow junction is disclosed including the steps of forming a gate and a gate insulating film on a semiconductor substrate of a first conductivity type, sequentially; formin...	07/22/1997
5504016	Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions The effect of dopant-dopant interaction on diffusion in silicon for a specific set of impurities is modeled. The first step in the modeling process involved quantum chemical calculations. The connection between the atomic scale results and macroscopic beh...	04/02/1996
5340752	Method for forming a bipolar transistor using doped SOG A method for forming a bipolar transistor which employs a single drive-in step to form an emitter and a base. A layer of SOG containing a plurality of dopants is spun onto a collector, typically silicon. The dopants are driven into the collector to form t...	08/23/1994
5324686	Method of manufacturing semiconductor device using hydrogen as a diffusion controlling substance A method of manufacturing a semiconductor device, which comprises the steps of forming a solid phase diffusion source containing a conductive impurity on a surface of a semiconductor substrate, said impurity serving to enable said semiconductor substrate ...	06/28/1994
5086005	Bipolar transistor and method for manufacturing the same In a self-alignment type-lateral bipolar transistor and a manufacturing method thereof, the base width is determined not by the image resolution limit of the lithography technique, as in the prior art, but by the impurity diffusion from the polysilicon la...	02/04/1992
5081050	Method of making a gate turn-off thyristor using a simultaneous diffusion of two different acceptor impurities In a high-reverse-voltage GTO thyristor, a negative beveling (6) with comparatively high beveling angle (଱) is possible as edge contouring as a result of separating the p-type base layer into a central p-type base layer (4) of small depth and high e...	01/14/1992
5063168	Process for making bipolar transistor with polysilicon stringer base contact There is disclosed herein a process for making a base and emitter contact structure for a bipolar transistor which is comprised of a polysilicon stripe over an isolation island which stripe extends to a position external to the position of the isolation i...	11/05/1991
4997774	Method for fabricating a DRAM cell This invention is related to a method for fabricating a DRAM cell. This invention makes the capacitor electrode and the source of the transistor connect more easily using the lateral diffusion of another dopant having higher diffusivity and same impurity ...	03/05/1991
4939103	Method of diffusing plurality of dopants simultaneously from vapor phase into semiconductor substrate This invention relates to the manufacture of semiconductor devices and more particularly to a method of diffusing an impurity layer into a substrate. The disclosed method comprises the steps of placing a body of semiconductor in a vacuum doping chamber, e...	07/03/1990
4830983	Method of enhanced introduction of impurity species into a semiconductor structure from a deposited source and application thereof A two step annealing process is utilized for performing imputity induced disordering comprising an initial higher temperature, shorter term or rapid thermal anneal (RTA) treatment followed by a lower temperature, longer term or slow thermal anneal (STA) t...	05/16/1989
4820656	Method for producing a p-doped semiconductor region in an n-conductive semiconductor body A method for producing a p-doped semiconductor region in an n-conductive semiconductor body by means of diffusion using a combination of both aluminum and boron as dopants. The semiconductor body is positioned within a hollow silicon member which itself i...	04/11/1989
4778772	Method of manufacturing a bipolar transistor A method of manufacturing a semiconductor device by forming an N type collector layer in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains...	10/18/1988
4629520	Method of forming shallow n-type region with arsenic or antimony and phosphorus A method of forming a shallow n-type region of a semiconductor device, such as a bipolar transistor or a MOS FET, includes the following steps. Forming a first film containing arsenic or antimony on a silicon substrate; forming a second film containing ph...	12/16/1986
4609414	Emitter finger structure in a switching transistor A particular emitter finger structure in an NPN type switching transistor. The emitter zone is divided into two lateral N type strips. In the central part are provided, on the one hand, a diffusion of N type dopants whose junction depth is small and, on t...	09/02/1986
4597824	Method of producing semiconductor device A method of producing a MOS transistor of LDD structure with p(n) type pockets. A doped oxide film in which impurities such as phosphorus and impurities such as arsenic are doped is formed on a semiconductor substrate, and a nitride film is formed in regi...	07/01/1986
4589936	Method for fabricating a semiconductor device by co-diffusion of arsenic and phosphorus A semiconductor device is fabricated by selectively providing on a surface of a semiconductor body a plurality of impurity diffusion sources each containing an n-type impurity comprising phosphorus and arsenic, at least two of said impurity diffusion sour...	05/20/1986
4344980	Superior ohmic contacts to III-V semiconductor by virtue of double donor impurity A method for fabricating superior ohmic contacts in a III-V semiconductor wafer by virtue of double donor (or double acceptor) impurity complex formation. A typical III-V, e.g., GaAs, semiconductor device is fabricated by depositing a thin Si3 ...	08/17/1982
4338481	Very thin silicon wafer base solar cell The performance and ruggedness of very thin silicon back surface field (BSF) solar cells are improved by the formation of a relatively thick, epitaxially grown, highly doped layer at the back of the cell and the formation of an arsenic doped layer at the ...	07/06/1982
4296426	Process for producing an MOS-transistor and a transistor produced by this process A process for producing a field-effect insulated-gate transistor of the N-channel MOS-type, transistor comprising, on a semiconductor substrate, a control gate (14) and a source region (12), a drain region (13) and a channel region (15, 16), which compris...	10/20/1981

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Class 438/547 - Simultaneously