Class 438/546 - Plural dopants in same region (e.g., through same mask opening, etc.)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes for applying multiply electrically active impurities
No. of patents: 141
Last issue date: 03/06/2012

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Number	Title	Issue Date
8129262	Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage Fabrication of an insulated-gate field-effect transistor (110) entails separately introducing three body-material dopants, typically through an opening in a mask, into body material (50) of a semiconductor body so as to reach respective maximum dopant ...	03/06/2012
7972948	Method for forming bit lines for semiconductor devices A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the sec...	07/05/2011
7811915	Method for forming bit lines for semiconductor devices A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer,...	10/12/2010
7807555	Method of forming the NDMOS device body with the reduced number of masks This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an...	10/05/2010
7585753	Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc...	09/08/2009
7429496	Buried photodiode for image sensor with shallow trench isolation technology A buried photodiode with shallow trench isolation technology is formed in a semiconductor substrate of a first conductive type. A trench having a bottom portion and a sidewall portion is formed in the semiconductor substrate. An isolation region is formed on the bot...	09/30/2008
7332439	Metal gate transistors with epitaxial source and drain regions An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor. ...	02/19/2008
7301221	Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc...	11/27/2007
7297617	Method for controlling diffusion in semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc...	11/20/2007
7262110	Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ...	08/28/2007
7235498	Process for growing a dielectric layer on a silicon-containing surface using a mixture of NO and O This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance gr...	06/26/2007
7202146	Process for producing doped semiconductor wafers from silicon, and the wafers produced thereby A process for producing doped semiconductor wafers from silicon, which contain an electrically active dopant, such as boron, phosphorus, arsenic or antimony, optionally are additionally doped with germanium and have a defined thermal conductivity, involves producing...	04/10/2007
7157779	Semiconductor device with triple surface impurity layers An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A...	01/02/2007
7138322	Semiconductor device and fabrication method therefor An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and ar...	11/21/2006
7005364	Method for manufacturing semiconductor device The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern. The method for manufacturing a semiconductor device in...	02/28/2006
7005340	Method for manufacturing semiconductor device A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps. The method comprises the steps of: (a) forming a first mask layer...	02/28/2006
6984590	Method of manufacturing an EEPROM device A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion i...	01/10/2006
6936527	Low voltage non-volatile memory cell A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a progra...	08/30/2005
6927137	Forming a retrograde well in a transistor to enhance performance of the transistor A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A fir...	08/09/2005
6887745	Polysilicon thin film transistor and method of forming the same A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, ...	05/03/2005
6864144	Method of stabilizing resist material through ion implantation A resist material used to mask an underlying layer during an etch process is subjected to ion implantation to harden the resist material against damage from the etch process. In a particular embodiment, the resist material is compatible with exposure to 193 nm radia...	03/08/2005
6849528	Fabrication of ultra shallow junctions from a solid source with fluorine implantation One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the...	02/01/2005
6797594	Semiconductor device and method of manufacturing the same In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-t...	09/28/2004
6797597	Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of region...	09/28/2004
6773976	Semiconductor device and method for manufacturing the same A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation ar...	08/10/2004
6713351	Double diffused field effect transistor having reduced on-resistance A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of t...	03/30/2004
6680250	Formation of deep amorphous region to separate junction from end-of-range defects A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain...	01/20/2004
6645820	Polycrystalline silicon diode string for ESD protection of different power supply connections An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit...	11/11/2003
6579782	Vertical power component manufacturing method A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant ...	06/17/2003
6537899	Semiconductor device and a method of fabricating the same The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film 3, a gate insul...	03/25/2003
6489203	Stacked LDD high frequency LDMOSFET A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. T...	12/03/2002
6448589	Single side contacts for a semiconductor device A connector block formed in a semiconductor chip to provide all contacts on the same side of the chip. The connector block is preferably formed by driving a slow diffusing dopant deep into the chip from both sides until the diffused dopant overlaps in the...	09/10/2002
6380038	Transistor with electrically induced source/drain extensions A method of fabricating an integrated circuit provides a transistor having less susceptibility to short channel effects. The transistor utilizes a U-shaped gate conductor and a main gate conductor. The U-shaped gate conductor can provide electrically indu...	04/30/2002
6362056	Method of making alternative to dual gate oxide for MOSFETs A method for forming depleted conductor regions in MOSFET arrays includes the steps of preparing a substrate, forming a conductor layer on the substrate, implanting a dopant species into the conductor layer, masking portions of the doped conductor layer, ...	03/26/2002
6362039	Self-aligned resistor and local interconnect A method is provided for combining the process steps for forming a resistor and interconnect into one process layer, thus eliminating the need for at least two mask steps. An oxide layer is formed over a region of a polysilicon layer in which the resistor...	03/26/2002
6362019	Solid-state imaging device and manufacturing method therefor A solid-state imaging device comprises a plurality of pixels, each pixel comprising a semiconductor substrate of a first conductivity type; a photo-receiving portion of a second conductivity type formed in the semiconductor substrate; a detecting portion ...	03/26/2002
6342438	Method of manufacturing a dual doped CMOS gate A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows a...	01/29/2002
6342418	Semiconductor device and manufacturing method thereof An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a s...	01/29/2002
6316341	Method for cell pass transistor design in DRAM process A method for forming a cell passes transistor in DRAM process disclosed. In one embodiment, the present invention provides a MOS structure, which can reduce junction leakage for P/N junction and increase the refreshes time capability. A method for DRAM fa...	11/13/2001
6313002	Ion-implantation method applicable to manufacture of a TFT for use in a liquid crystal display apparatus The present invention relates to a method of manufacturing a thin film transistor for use in a liquid crystal display apparatus or the like. In the method, impurity ions are implanted into a semiconductor by intermittently generating a plasma which genera...	11/06/2001

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Class 438/546 - Plural dopants in same region (e.g., through same mask opening, etc.)