"The idea that cavalry will be replaced by these iron coaches is absurd. It is little short of treasonous."
Aide-de-camp to Field Marshal Haig ; At a tank demonstration, 1916
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| Number | Title | Issue Date |
| 7897497 | Overvoltage-protected light-emitting semiconductor device, and method of fabrication A light-generating semiconductor region is grown by epitaxy on a silicon substrate. The light-generating semiconductor region is a lamination of layers of semiconducting nitrides containing a Group III element or elements. The silicon substrate has a p-type impurity... | 03/01/2011 |
| 7261835 | Acid blend for removing etch residue A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, ... | 08/28/2007 |
| 7247921 | Semiconductor apparatus and method of manufacturing same, and method of detecting defects in semiconductor apparatus A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semic... | 07/24/2007 |
| 7166186 | Laser decapsulation apparatus and method A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X,Y table 2. A hi... | 01/23/2007 |
| 7144796 | Method of fabricating semiconductor components through implantation and diffusion in a semiconductor substrate A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least o... | 12/05/2006 |
| 7131436 | Engine ignition system having noise protection circuit An ignition system for an internal combustion engine is connected to an ignition coil and to a circuit for providing an ignition signal. The ignition system includes a switch circuit connected to the ignition coil that switches on or off current supplied to the igni... | 11/07/2006 |
| 6936527 | Low voltage non-volatile memory cell A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a progra... | 08/30/2005 |
| 6756270 | Semiconductor device and fabrication method thereof A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad ... | 06/29/2004 |
| 6727527 | Reverse blocking IGBT A power device includes a semiconductor substrate of first conductivity type. The semiconductor substrate includes a front-side surface, a backside surface, and a scribe region. The substrate has a first well of second conductivity type whereon an active cell is def... | 04/27/2004 |
| 6706606 | Buried zener diode structure and method of manufacture A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface. ... | 03/16/2004 |
| 6696335 | Method for forming a diffusion region For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantial... | 02/24/2004 |
| 6635505 | Method of manufacturing an active matrix type semiconductor display device There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, diffe... | 10/21/2003 |
| 6579782 | Vertical power component manufacturing method A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant ... | 06/17/2003 |
| 6569691 | Measurement of different mobile ion concentrations in the oxide layer of a semiconductor wafer A method and apparatus for measuring the concentration of different mobile ions in the oxide layer of a semiconductor wafer from the contact potential shift caused by different ions drifting across the oxide that includes depositing charge (e.g., using a ... | 05/27/2003 |
| 6559019 | Breakdown drain extended NMOS An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conduc... | 05/06/2003 |
| 6475861 | Semiconductor device and fabrication method thereof A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the... | 11/05/2002 |
| 6455380 | Semiconductor device and method for fabricating the same A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region in... | 09/24/2002 |
| 6444522 | Method of manufacturing a flash memory device with an antidiffusion region between well regions There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a break down voltage between wells is reduced and an insulating characteristic between the wells is lowered due to degraded barrier characteristic betw... | 09/03/2002 |
| 6436769 | Split gate flash memory with virtual ground array structure and method of fabricating the same The present invention provides a flash memory having a split gate structure and virtual ground array structure, wherein a high impurity concentration region of a first conductivity type is provided in a drain adjacent region of a channel region under a fl... | 08/20/2002 |
| 6429077 | Method of forming a lateral diffused metal-oxide semiconductor transistor The present invention provides a method of forming a lateral diffused metal-oxide semiconductor (LD MOS) transistor on a semiconductor wafer. An ion implantation process is performed on a predetermined area of the silicon substrate so as to form a p-well ... | 08/06/2002 |
| 6391689 | Method of forming a self-aligned thyristor A semiconductor substrate having a doped well region is provided. A gate stacking structure is formed on the doped well region. The gate stacking structure divides the doped well region into a first area and a second area. The second area is masked. The f... | 05/21/2002 |
| 6368928 | Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semi... | 04/09/2002 |
| 6345399 | Hard mask process to prevent surface roughness for selective dielectric etching The propagation of microfissures from a photoresist to an underlying material layer during lithography and etching can be substantially prevented by placing a hard mask between the photoresist and the material layer to be etched. Specifically, the microfi... | 02/12/2002 |
| 6329272 | Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent re... | 12/11/2001 |
| 6238985 | Semiconductor device and method for fabricating the same A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region in... | 05/29/2001 |
| 6232182 | Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region ... | 05/15/2001 |
| 6207540 | Method for manufacturing high performance MOSFET device with raised source and drain A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion... | 03/27/2001 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6169001 | CMOS device with deep current path for ESD protection In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capabili... | 01/02/2001 |
| 6156594 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, ope... | 12/05/2000 |
| 6150671 | Semiconductor device having high channel mobility and a high breakdown voltage for high power applications A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source reg... | 11/21/2000 |
| 6136673 | Process utilizing selective TED effect when forming devices with shallow junctions A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same re... | 10/24/2000 |
| 6103613 | Method for fabricating semiconductor components with high aspect ratio features A method for fabricating an interconnect with high aspect ratio contact members is provided. The interconnect is adapted to make electrical connections with a semiconductor component, such as a die, a wafer, or a chip scale package for testing. The method... | 08/15/2000 |
| 6025235 | Short channel transistor having resistive gate extensions A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide reg... | 02/15/2000 |
| 5998268 | Manufacturing method of semiconductor device with a groove On the surface of a semiconductor substrate there are formed a silicon oxide film, silicon nitride film and resist, whereby a groove is formed in the semiconductor substrate through an opening portion by chemical dry etching. An oxide film is formed on th... | 12/07/1999 |
| 5985728 | Silicon on insulator process with recovery of a device layer from an etch stop layer A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the et... | 11/16/1999 |
| 5897355 | Method of manufacturing insulated gate semiconductor device to improve ruggedness An insulated gate field effect transistor is manufactured according to a process in which an insulated gate structure is formed along a semiconductor chip. Dopant is introduced into the chip to form a body region, semiconductor material outside the body r... | 04/27/1999 |
| 5888889 | Integrated structure pad assembly for lead bonding A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active... | 03/30/1999 |
| 5877044 | Method of making MOS-gated semiconductor devices A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholl... | 03/02/1999 |
| 5851866 | Fabrication method for CMOS with sidewalls A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current dri... | 12/22/1998 |