Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 7851339 | Method of repairing deep subsurface defects in a silicon substrate that includes diffusing negatively charged ions into the substrate from a sacrificial oxide layer Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating co... | 12/14/2010 |
| 7332750 | Power semiconductor device with improved unclamped inductive switching capability and process for forming same A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers ... | 02/19/2008 |
| 7317242 | Semiconductor device including p-type silicon layer including implanted germanium The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower im... | 01/08/2008 |
| 7259440 | Fast switching diode with low leakage current A fast switching diode includes an n− layer having an upper surface and a lower surface and a first edge and a second edge, the second edge provided on an opposing side of the first edge. A converted region is provided proximate the upper surface of the n− layer... | 08/21/2007 |
| 7247513 | Dissociation of silicon clusters in a gas phase during chemical vapor deposition homo-epitaxial growth of silicon carbide A method of forming a layer of silicon carbide wherein silicon clusters are dissociated in a gas phase. Silicon clusters may be dissociated by a silicon-etching gas such as a group VII-containing component. A semiconductor device is also disclosed having a layer for... | 07/24/2007 |
| 7163854 | Fabrication method of a semiconductor device To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having a... | 01/16/2007 |
| 7122436 | Techniques for forming passive devices during semiconductor back-end processing Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked ... | 10/17/2006 |
| 7092609 | Method to realize fast silicon-on-insulator (SOI) optical device A fast silicon-on-insulator (SOI) waveguide-based optical device enhanced with minority charge carrier lifetime modifiers enables faster modulation speeds in optical attenuators, optical intensity/phase-modulators, and optical switches whose operation principles are... | 08/15/2006 |
| 7087981 | Metal semiconductor contact, semiconductor component, integrated circuit arrangement and method The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive meta... | 08/08/2006 |
| 7087507 | Implantation of deuterium in MOS and DRAM devices A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations ... | 08/08/2006 |
| 7061058 | Forming a retrograde well in a transistor to enhance performance of the transistor A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A fir... | 06/13/2006 |
| 6936527 | Low voltage non-volatile memory cell A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a progra... | 08/30/2005 |
| 6927141 | Process for forming fast recovery diode with a single large area P/N junction A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periph... | 08/09/2005 |
| 6878579 | Semiconductor device and method of manufacturing the same An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconduct... | 04/12/2005 |
| 6838321 | SEMICONDUCTOR SUBSTRATE WITH DEFECTS REDUCED OR REMOVED AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE CAPABLE OF BIDIRECTIONALLY RETAINING BREAKDOWN VOLTAGE AND METHOD OF MANUFACTURING THE SAME An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion layer (3) of high conce... | 01/04/2005 |
| 6815319 | Damascene resistor and method for measuring the width of same A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped regio... | 11/09/2004 |
| 6770519 | Semiconductor manufacturing method using two-stage annealing A method of semiconductor device manufacture provided includes forming a gate insulating layer upon a single crystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting impurity in the ... | 08/03/2004 |
| 6695903 | Dopant pastes for the production of p, p+, and n, n+ regions in semiconductors The invention relates to novel boron, phosphorus or boron-aluminium dopant pastes for the production of p, p+ and n, n+ regions in monocrystalline and polycrystalline Si wafers, and of corresponding pastes for use as masking pastes in semiconductor fabric... | 02/24/2004 |
| 6495891 | Transistor having impurity concentration distribution capable of improving short channel effect A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel re... | 12/17/2002 |
| 6475876 | Process for fabricating a semiconductor component In a process for fabricating a semiconductor component, in particular a semiconductor diode, a semiconductor substrate (1) is provided with metal layers (3, 4) in order to form electrode terminals and with passivation (2), and is exposed to particle irrad... | 11/05/2002 |
| 6469368 | Method for producing a high-speed power diode with soft recovery, and a power diode produced using such a method In a method for producing a high-speed power diode with soft recovery, in which method the carrier life within the associated semiconductor substrate (10) is governed by first, unmasked bombardment (14) with an axial profile and by subsequent, second, mas... | 10/22/2002 |
| 6459141 | Method and apparatus for suppressing the channeling effect in high energy deep well implantation The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then for... | 10/01/2002 |
| 6358825 | Process for controlling lifetime in a P-I-N diode and for forming diode with improved lifetime control In an improved process for controlling and improving minority carrier lifetime in a P-i-N diode, platinum is deposited on a surface of a silicon semiconductor substrate containing at least one PN junction. The substrate is heated to a temperature of about... | 03/19/2002 |
| 6248627 | Method for protecting gate edges from charge gain/loss in semiconductor device A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protec... | 06/19/2001 |
| 6159830 | Process for adjusting the carrier lifetime in a semiconductor component In a process for adjusting the carrier lifetime in a semiconductor component (1) by means of particle irradiation (P), at least two defect regions (10, 11, 12, 13) are produced in the semiconductor component (1). In this process, a particle beam (P), cons... | 12/12/2000 |
| 6143632 | Deuterium doping for hot carrier reliability improvement A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and... | 11/07/2000 |
| 6043112 | IGBT with reduced forward voltage drop and reduced switching loss The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.... | 03/28/2000 |
| 5966627 | In-situ doped silicon layers A method and apparatus for the manufacture of integrated circuits including the placement of a single tube for introduction of dopant gases into a process chamber is disclosed.... | 10/12/1999 |
| 5856231 | Process for producing high-resistance silicon carbide A process for producing high-resistance SiC from low-resistance SiC starting material. The flat (shallow) donor levels of a prevailing nitrogen impurity are overcompensated by admixture of a trivalent doping element with the concentration of the doping el... | 01/05/1999 |
| 5747371 | Method of manufacturing vertical MOSFET A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first reg... | 05/05/1998 |
| 5371040 | Method for manufacturing semiconductor components with short switching time A method is described for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area in contact with a PN junction. In order to obtain an inhomogeneous impurity distribution in the axial direction of the sem... | 12/06/1994 |
| 5300453 | Method for producing semiconductor device A method for producing a semiconductor device, is composed of steps of: covering a lower side of a semiconductor wafer with a heavy metal and disposing the semiconductor wafer in a chamber; causing the heavy metal to diffuse into the semiconductor wafer b... | 04/05/1994 |
| 5283202 | IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 02/01/1994 |
| 5032540 | A Process for modulating the quantity of gold diffused into a silicon substrate For modulating the quantity of gold diffused in a silicon substrate, prior to gold diffusion, one realizes a diffusion of phosphorus varying within a 1013 to 1015 atoms/cm3 range. The concentration of phosphorous is increa... | 07/16/1991 |
| 4963509 | Gold diffusion method for semiconductor devices of high switching speed Gold is diffused into a silicon substrate by first depositing an ultrathin layer of gold on one of the main faces of the substrate and then by heating the substrate to a temperature range of about 300°-850° C., instead of to about 1000° according to ... | 10/16/1990 |
| 4960731 | Method of making a power diode with high reverse voltage rating In making a power diode with high reverse voltage rating, corrosion of the silicon wafer surface by gettering substances is avoided by employing two different diffusion steps. In the first step, boron and phosphorus are respectively applied to opposing ma... | 10/02/1990 |
| 4935386 | Method of manufacturing semiconductor device including substrate bonding and outdiffusion by thermal heating A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of ... | 06/19/1990 |
| 4925812 | Platinum diffusion process Platinum atoms are uniformly dispersed throughout a silicon wafer containing preformed junctions by depositing a layer of platinum on a clean silicon surface and thereafter immediately heating the wafer to about 500° C. to form platinum silicide. Alterna... | 05/15/1990 |
| 4613381 | Method for fabricating a thyristor In a method for fabricating a thyristor in which n-type impurities are diffused in a p-base of a pnp wafer to form an n+ -emitter, the step of diffusing the n-type impurities for forming the n+ -emitter has the conditions which are s... | 09/23/1986 |
| 4609414 | Emitter finger structure in a switching transistor A particular emitter finger structure in an NPN type switching transistor. The emitter zone is divided into two lateral N type strips. In the central part are provided, on the one hand, a diffusion of N type dopants whose junction depth is small and, on t... | 09/02/1986 |
