Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8039377 | Semiconductor constructions Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage... | 10/18/2011 |
| 7790588 | Dual gate of semiconductor device capable of forming a layer doped in high concentration over a recessed portion of substrate for forming dual gate with recess channel structure and method for manufacturing the same A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type Si... | 09/07/2010 |
| 7763531 | Method and structure to process thick and thin fins and variable fin to fin spacing The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fi... | 07/27/2010 |
| 7407850 | N+ poly on high-k dielectric for semiconductor devices The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is per... | 08/05/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7314812 | Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for e... | 01/01/2008 |
| 7307008 | Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell ... | 12/11/2007 |
| 7291546 | Method and apparatus for reducing charge loss in a nonvolatile memory cell A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate desi... | 11/06/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7259070 | Semiconductor devices and methods for fabricating the same Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in th... | 08/21/2007 |
| 7230303 | Semiconductor memory device with reduced soft error rate (SER) and method for fabricating same The present invention provides a semiconductor memory device with reduced soft error rate (SER) and a method for fabricating such a device. The semiconductor memory device includes a plurality of implants of impurity ions that provide for a reduced number of minorit... | 06/12/2007 |
| 7223649 | Method of fabricating transistor of DRAM semiconductor device Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an a... | 05/29/2007 |
| 7211523 | Method for forming field oxide A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substra... | 05/01/2007 |
| 7189623 | Semiconductor processing method and field effect transistor A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed ... | 03/13/2007 |
| 7186631 | Method for manufacturing a semiconductor device Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon;... | 03/06/2007 |
| 7148151 | Dry etching method, fabrication method for semiconductor device, and dry etching apparatus When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically,... | 12/12/2006 |
| 7118973 | Method of forming a transistor with a channel region in a layer of composite material The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is... | 10/10/2006 |
| 7115959 | Method of forming metal/high-k gate stacks with high mobility The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the ga... | 10/03/2006 |
| 7098095 | Method of forming a MOS transistor with a layer of silicon germanium carbon The vertical diffusion of dopants from the gate into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming ... | 08/29/2006 |
| 7098140 | Method of compensating for etch rate non-uniformities by ion implantation Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this ... | 08/29/2006 |
| 7091116 | Methods of manufacturing semiconductor devices Disclosed is an example method of manufacturing a semiconductor device. The disclosed example method includes depositing a gate insulating layer on an active region of a self aligned silicide (salicide) region and a non-self aligned silicide (salicide) region of a s... | 08/15/2006 |
| 7087509 | Method of forming a gate electrode on a semiconductor device and a device incorporating same The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative e... | 08/08/2006 |
| 7064034 | Technique for fabricating logic elements using multiple gate layers Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and mem... | 06/20/2006 |
| 7061031 | High-sensitivity image sensor and fabrication method thereof A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-... | 06/13/2006 |
| 7052955 | Semiconductor memory device and manufacturing method thereof A method for manufacturing a semiconductor device including an electrode having a lower silicon layer and an upper silicon layer which is formed on the lower silicon layer. A concentration of impurities in the upper silicon layer is higher than a concentration of im... | 05/30/2006 |
| 7045427 | Polysilicon gate doping level variation for reduced leakage current A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region. ... | 05/16/2006 |
| 7030444 | Space process to prevent the reverse tunneling in split gate flash A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over t... | 04/18/2006 |
| 6977204 | Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do... | 12/20/2005 |
| 6972232 | Method of manufacturing a semiconductor device There is provided a method of manufacturing a high quality P-channel trench MOSFET which stably operates. In the method of manufacturing a P-channel trench MOSFET having a P-type gate electrode, the process in which BF2 ions are implanted into a polycryst... | 12/06/2005 |
| 6927152 | Method for fabricating semiconductor device The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: 1. A method for fabricating a semiconductor device, which comprises the steps of: forming a gate line on a semiconductor substrate; forming junction ... | 08/09/2005 |
| 6919247 | Method of fabricating a floating gate A method of fabricating a floating gate for a semiconductor device is disclosed and provided. According to this method, an undoped polycrystalline silicon layer is deposited on a tunnel oxide layer. The undoped polycrystalline silicon layer has a first thickness. Mo... | 07/19/2005 |
| 6911381 | Boron incorporated diffusion barrier material A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. ... | 06/28/2005 |
| 6908803 | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate ... | 06/21/2005 |
| 6878601 | Method for fabricating a capacitor containing metastable polysilicon Described is a method for fabricating a capacitor of a semiconductor device. The method includes the steps of forming an insulating interlayer including a storage node contact hole on a semiconductor substrate, forming a polysilicon layer on the insulating interlaye... | 04/12/2005 |
| 6867113 | In-situ deposition and doping process for polycrystalline silicon layers and the resulting device An in-situ deposition and doping method for polycrystalline silicon layers of semiconductor devices. A first intermediate layer of in-situ doped polycrystalline silicon is grown, and a second additional layer of polycrystalline silicon is grown with a lower doping l... | 03/15/2005 |
| 6855605 | Semiconductor device with selectable gate thickness and method of manufacturing such devices A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts... | 02/15/2005 |
| 6841441 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate... | 01/11/2005 |
| 6773987 | Method and apparatus for reducing charge loss in a nonvolatile memory cell A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate desi... | 08/10/2004 |
| 6750122 | Semiconductor device formed with an oxygen implant step A method of forming a semiconductor structure (see e.g., FIG. 3) includes forming a silicon (e.g., polysilicon) layer 14. The silicon layer 14 is patterned and etched so that at least one sidewall 20 is exposed. An oxygen bearing species ... | 06/15/2004 |
