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| Number | Title | Issue Date |
| 8163637 | Forming impurity regions in silicon carbide devices First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor r... | 04/24/2012 |
| 8067302 | Defect-free junction formation using laser melt annealing of octadecaborane self-amorphizing implants A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then melted, resolidified, and annealed to completely dissociate ... | 11/29/2011 |
| 8043947 | Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associate... | 10/25/2011 |
| 8008175 | Semiconductor structure made using improved simultaneous multiple ion implantation process Methods and apparatus provide for: a first source of plasma (first plasma), which includes a first species of ions, directing the first plasma out along a first axis; a second source of plasma (second plasma), which includes a second, differing, species of ions, dir... | 08/30/2011 |
| 7968441 | Dopant activation anneal to achieve less dopant diffusion (better USJ profile) and higher activation percentage A method and apparatus for forming a semiconductor device. A semiconductor substrate is implanted with dopants. The substrate is subjected to a cleaning process employing electrically neutral nitrogen and fluorine radicals to produce an oxygen-free surface having da... | 06/28/2011 |
| 7939441 | P-type silicon wafer and method for heat-treating the same This p-type silicon wafer was subjected to heat treatment to have a resistivity of 10 Ω·cm or more, a BMD density of 5×107 defects/cm3 or more, and an n-type impurity concentration of 1×1014 atoms/cm3 or less at a dept... | 05/10/2011 |
| 7923361 | Method for manufacturing a semiconductor integrated circuit device The resist film after high-concentration ion implantation has a hard modified layer on the surface thereof, and is difficult to remove in the temperature region as low as about 150 degrees centigrade. This is because the etching rate of the modified layer sharply de... | 04/12/2011 |
| 7888250 | Method and apparatus for activating compound semiconductor A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The... | 02/15/2011 |
| 7879704 | Memory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each parti... | 02/01/2011 |
| 7842590 | Method for manufacturing a semiconductor substrate including laser annealing A method for manufacturing a semiconductor device by laser annealing. One embodiment provides a semiconductor substrate having a first surface and a second surface. The second surface is arranged opposite to the first surface. A first dopant is introduced into the s... | 11/30/2010 |
| 7807554 | Method of manufacturing semiconductor element A method of manufacturing a semiconductor element includes implanting ions of a dopant having a large diffusion coefficient into a semiconductor to provide a doped layer; and irradiating the doped layer with a plurality of pulsed laser beams supplied by a plurality ... | 10/05/2010 |
| 7795122 | Antimony ion implantation for semiconductor components A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to ... | 09/14/2010 |
| 7790587 | Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal ... | 09/07/2010 |
| 7741200 | Formation and treatment of epitaxial layer containing silicon and carbon Methods for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment converts interstitial carbon to substitutional carbon in the epitaxial layer, according to one or more embodiments. Specific embodiments pertain to the for... | 06/22/2010 |
| 7704865 | Methods of forming charge-trapping dielectric layers for semiconductor memory devices Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in... | 04/27/2010 |
| 7682955 | Method for forming deep well of power device The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a ... | 03/23/2010 |
| 7674696 | Method of fabricating semiconductor device In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A... | 03/09/2010 |
| 7611976 | Gate electrode dopant activation method for semiconductor manufacturing Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a do... | 11/03/2009 |
| 7560367 | Method for thermal processing with a RTP process using temperature spaces in radiation equilibrium In this invention, a wafer is placed and kept in the low-temperature region at the bottom of a temperature space that is in a state of radiation equilibrium and that is formed inside chamber by a heating unit. The substrate temperature is gradually raised to a tempe... | 07/14/2009 |
| 7550371 | Method of producing SIMOX wafer A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere... | 06/23/2009 |
| 7507647 | Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer... | 03/24/2009 |
| 7452793 | Wafer curvature estimation, monitoring, and compensation A method of determining wafer curvature in real-time is presented. The method includes establishing a first temperature profile for a hotplate surface, where the hotplate surface is divided into a plurality of temperature control zones. The method further includes p... | 11/18/2008 |
| 7442632 | Semiconductor device n-channel type MOS transistor with gate electrode layer featuring small average polycrystalline silicon grain size In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickne... | 10/28/2008 |
| 7429514 | Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t... | 09/30/2008 |
| 7419893 | Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated This patent specification describes methods for fabricating semiconductor device having a plurality of well structures including a triple-well structure. One example of a method for fabricating semiconductor device includes forming a thermally stable film on a first... | 09/02/2008 |
| 7413968 | Method of manufacturing semiconductor device having gate electrodes of polymetal gate and dual-gate structure A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities impl... | 08/19/2008 |
| 7396717 | Method of forming a MOS transistor A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the... | 07/08/2008 |
| 7396482 | Post exposure resist bake A preferred embodiment of the invention provides a method for forming an integrated circuit. The method comprises forming a resist layer on a substrate. Preferably, the photoresist layer comprises a photo acid generator (PAG). Embodiments include irradiating the res... | 07/08/2008 |
| 7358200 | Gas-assisted rapid thermal processing A system, method and apparatus for processing a semiconductor device including a processing chamber and a heating assembly positioned within the processing chamber. The heating assembly including at least a plate defining an internal cavity configured to receive gas... | 04/15/2008 |
| 7358167 | Implantation process in semiconductor fabrication A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a ... | 04/15/2008 |
| 7354836 | Technique for forming a strained transistor by a late amorphization and disposable spacers By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as lase... | 04/08/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7341787 | Process for producing highly doped semiconductor wafers, and dislocation-free highly doped semiconductor wafers The invention relates to a process for producing highly doped semiconductor wafers, in which at least two dopants which are electrically active and belong to the same group of the periodic system of the elements are used for the doping. The invention also relates to... | 03/11/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7335611 | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on... | 02/26/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7320929 | Method of fabricating SOI wafer In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the ... | 01/22/2008 |
| 7316970 | Method for forming high selectivity protection layer on semiconductor device A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is form... | 01/08/2008 |
| 7314812 | Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for e... | 01/01/2008 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
