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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 7939440 | Junction leakage suppression in memory devices A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric... | 05/10/2011 |
| 7867884 | Sample wafer fabrication method A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity con... | 01/11/2011 |
| 7678674 | Memory cell dual pocket implant A method of forming implants for a memory cell includes forming an oxide-nitride-oxide (ONO) stack over a substrate and implanting first impurities in the substrate adjacent each side of the ONO stack using a first implantation energy and a first tilt angle to produ... | 03/16/2010 |
| 7432121 | Isolation process and structure for CMOS imagers A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted reg... | 10/07/2008 |
| 7358167 | Implantation process in semiconductor fabrication A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a ... | 04/15/2008 |
| 7335581 | Semiconductor memory device and method of manufacturing the same A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and th... | 02/26/2008 |
| 7297579 | Semiconductor device and manufacturing method thereof The objectives of the present invention are achieving TFTs having a small off current and TFT structures optimal for the driving conditions of a pixel portion and driver circuits, and providing a technique of making the differently structured TFTs without increasing... | 11/20/2007 |
| 7294551 | Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for... | 11/13/2007 |
| 7291525 | System and method for manufacturing thin film resistors using a trench and chemical mechanical polishing A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the t... | 11/06/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7259072 | Shallow low energy ion implantation into pad oxide for improving threshold voltage stability A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ ... | 08/21/2007 |
| 7238600 | Semiconductor device and fabrication method thereof For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate... | 07/03/2007 |
| 7214592 | Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant ... | 05/08/2007 |
| 7211863 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 05/01/2007 |
| 7202536 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 04/10/2007 |
| 7195995 | Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area ... | 03/27/2007 |
| 7192823 | Manufacturing method for transistor of electrostatic discharge protection device A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be im... | 03/20/2007 |
| 7189623 | Semiconductor processing method and field effect transistor A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed ... | 03/13/2007 |
| 7186623 | Integrated semiconductor device and method of manufacturing thereof An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device inclu... | 03/06/2007 |
| 7179714 | Method of fabricating MOS transistor having fully silicided gate There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate ... | 02/20/2007 |
| 7172933 | Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate... | 02/06/2007 |
| 7172954 | Implantation process in semiconductor fabrication A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a ... | 02/06/2007 |
| 7166506 | Poly open polish process A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with hi... | 01/23/2007 |
| 7151015 | Semiconductor device and manufacturing method thereof There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration im... | 12/19/2006 |
| 7135738 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 11/14/2006 |
| 7126204 | Integrated semiconductor circuit with an electrically programmable switching element The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased wi... | 10/24/2006 |
| 7078325 | Process for producing a doped semiconductor substrate A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and acc... | 07/18/2006 |
| 7067365 | High-voltage metal-oxide-semiconductor devices and method of making the same An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of the high-voltage device area is not etched back before a high-dosage i... | 06/27/2006 |
| 7053452 | Metal oxide semiconductor device for electrostatic discharge protection circuit A MOS device for an electrostatic discharge protection circuit provided. A gate structure is disposed on the substrate. A source region and a drain region are formed in the substrate beside the gate structure. A doped layer is disposed underneath the source region a... | 05/30/2006 |
| 7041581 | Method and structure for improving latch-up immunity using non-dopant implants The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming a non-dopant region near the edge of a dopant region. The preferred embodiment ... | 05/09/2006 |
| 7030464 | Semiconductor device and method of manufacturing the same A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region for... | 04/18/2006 |
| 7022577 | Method of forming ultra shallow junctions The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an io... | 04/04/2006 |
| 7005334 | Zero threshold voltage pFET and method of making same A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent... | 02/28/2006 |
| 6995079 | Ion implantation method and method for manufacturing semiconductor device An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the ... | 02/07/2006 |
| 6987062 | Manufacturing method of semiconductor device This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is... | 01/17/2006 |
| 6984590 | Method of manufacturing an EEPROM device A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion i... | 01/10/2006 |
| 6977207 | Method for fabricating dual-gate semiconductor device A method for fabricating a dual-gate semiconductor device is disclosed. The method A method for fabricating a dual-gate semiconductor device, the method comprising the steps: forming field oxide films defining an active region and a field region on a semiconductor s... | 12/20/2005 |
| 6964906 | Programmable element with selectively conductive dopant and method for programming same A programmable element including a semiconductor material doped with a dopant that alters the resistance of the element when exposed to actinic radiation. Rather than producing a mechanical deformation, the radiation rearranges the bonding configuration of the dopan... | 11/15/2005 |
