Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8026160 | Semiconductor device and semiconductor device manufacturing method In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC e... | 09/27/2011 |
| 7981783 | Semiconductor device and method for fabricating the same A semiconductor device including at least one drift region formed near a channel region on a substrate, a first buried insulating layer formed in the drift region, and a first reduced surface field region interposed between the first buried insulating layer and the ... | 07/19/2011 |
| 7943497 | Method for manufacturing an SOI substrate A substrate surface serving as an SOI region and a substrate surface serving as a bulk region are made to form the same plane easily and highly accurately, a thickness of a buried oxide film is made uniform, and the buried oxide film is also prevented from being exp... | 05/17/2011 |
| 7863170 | Semiconductor body comprising a transistor structure and method for producing a transistor structure A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is differen... | 01/04/2011 |
| 7727867 | Method for manufacturing SIMOX wafer A MLD-SIMOX wafer is obtained by forming a first ion-implanted layer in a silicon wafer; forming a second ion-implanted layer that is in an amorphous state; and subjecting the wafer to a high-temperature heat treatment to maintain the wafer in an atmosphere containi... | 06/01/2010 |
| 7582546 | Device with damaged breakdown layer A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage. ... | 09/01/2009 |
| 7524744 | Method of producing SOI wafer and SOI wafer The present invention provides a method of producing an SOI wafer, comprising at least steps of forming an oxygen ion-implanted layer by implanting oxygen ions into a silicon wafer from one main surface thereof, subjecting the silicon wafer to oxide film-forming hea... | 04/28/2009 |
| 7514343 | Method for manufacturing SIMOX wafer and SIMOX wafer This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and... | 04/07/2009 |
| 7514344 | Lateral bipolar transistor A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which s... | 04/07/2009 |
| 7491632 | Buried subcollector for high frequency passive semiconductor devices A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provi... | 02/17/2009 |
| 7439110 | Strained HOT (hybrid orientation technology) MOSFETs A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semicon... | 10/21/2008 |
| 7410887 | Controlled process and resulting device A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surfa... | 08/12/2008 |
| 7354815 | Method for fabricating semiconductor devices using strained silicon bearing material A method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of mat... | 04/08/2008 |
| 7348257 | Process for manufacturing wafers of semiconductor material by layer transfer A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is... | 03/25/2008 |
| 7348225 | Structure and method of fabricating FINFET with buried channel A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first materi... | 03/25/2008 |
| 7332763 | Selective coupling of voltage feeds for body bias voltage in an integrated circuit device An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupl... | 02/19/2008 |
| 7334198 | Software controlled transistor body bias Software controlled body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasin... | 02/19/2008 |
| 7330369 | NANO-electronic memory array Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying ... | 02/12/2008 |
| 7326983 | Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into ... | 02/05/2008 |
| 7320929 | Method of fabricating SOI wafer In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the ... | 01/22/2008 |
| 7311850 | Method of forming patterned thin film and method of fabricating micro device In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface... | 12/25/2007 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7294564 | Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said lay... | 11/13/2007 |
| 7294578 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 11/13/2007 |
| 7291849 | Calibration standard for transmission electron microscopy A calibration standard includes a silicon substrate having a plurality of defined regions and a plurality of calibration marks placed on respective defined regions of the silicon substrate. Each calibration mark comprises a different calibration dimension indicator ... | 11/06/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7271080 | Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same are provided. An EEPROM cell includes an isolation layer formed at a semiconductor substrate to define an active region. A source region, a buried N+ region and a ... | 09/18/2007 |
| 7271447 | Semiconductor device A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semic... | 09/18/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7262113 | Methods for transferring a useful layer of silicon carbide to a receiving substrate Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the invention relates to a method for recycling of a silicon carbide source substrate by removal of the excess zone followed by a finishing step to p... | 08/28/2007 |
| 7256639 | Systems and methods for integrated circuits comprising multiple body bias domains Systems and methods for integrated circuits comprising multiple body bias domains. In accordance with a first embodiment of the present invention, an integrated circuit is constructed comprising active semiconductor devices in first and second body bias domains. A f... | 08/14/2007 |
| 7253062 | Semiconductor device with asymmetric pocket implants A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion regio... | 08/07/2007 |
| 7253073 | Structure and method for hyper-abrupt junction varactors A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various... | 08/07/2007 |
| 7244632 | Complementary metal oxide semiconductor image sensor and method for fabricating the same A complementary metal oxide semiconductor image sensor and a method for fabricating the same are disclosed, wherein a width of a depletion area of a photodiode is varied by variably applying a back bias voltage to a semiconductor substrate without using any color fi... | 07/17/2007 |
| 7232738 | Device and method for cutting an assembly A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assemb... | 06/19/2007 |
| 7228242 | Adaptive power control based on pre package characterization of integrated circuits A method and system of adaptive power control based on pre package characterization of integrated circuits. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit. ... | 06/05/2007 |
| 7220644 | Single-pole component manufacturing The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are ... | 05/22/2007 |
| 7221038 | Method of fabricating substrates and substrates obtained by this method Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous ... | 05/22/2007 |
| 7211478 | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described. ... | 05/01/2007 |
