Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8133804 | Method and system for modifying patterned photoresist using multi-step ion implantation A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line wi... | 03/13/2012 |
| 8039376 | Methods of changing threshold voltages of semiconductor transistors by ion implantation A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top... | 10/18/2011 |
| 7998849 | Semiconductor device used as high-speed switching device and power device A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conduc... | 08/16/2011 |
| 7981782 | Method of fabricating a semiconductor device including ion implantation at a tilt angle in exposed regions A method of fabricating a semiconductor device includes forming a mask pattern for exposing a region of a semiconductor substrate. Dopant ions are implanted into the exposed region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. ... | 07/19/2011 |
| 7977225 | Reducing implant degradation in tilted implantations by shifting implantation masks In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask ar... | 07/12/2011 |
| 7867883 | Methods of fabricating non-volatile memory devices A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implan... | 01/11/2011 |
| 7803701 | Method for fabricating a semiconductor device A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a ... | 09/28/2010 |
| 7785994 | Ion implantation method and semiconductor device manufacturing method In the ion implantation method and semiconductor device manufacturing method relating to the present invention, a disc on which multiple semiconductor substrates are mounted is positioned in the manner that a first angle β1 is made between an X-Y plane p... | 08/31/2010 |
| 7767562 | Method of implanting using a shadow effect A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surf... | 08/03/2010 |
| 7732310 | Sidewall memory with self-aligned asymmetrical source and drain configuration A method of forming a semiconductor structure includes providing a semiconductor substrate and forming a memory cell at a surface of the semiconductor substrate. The step of forming the memory cell includes forming a gate dielectric on the semiconductor substrate an... | 06/08/2010 |
| 7704864 | Method of manufacturing a superjunction device with conventional terminations A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched i... | 04/27/2010 |
| 7687384 | Semiconductor device and method for fabricating the same that includes angled implantation of poly layer Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a port... | 03/30/2010 |
| 7504327 | Method of manufacturing thin film semiconductor device In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode layer in a thin film transistor The semiconductor layer is doped obliq... | 03/17/2009 |
| 7442614 | Silicon on insulator devices having body-tied-to-source and methods of making Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer... | 10/28/2008 |
| 7429519 | Method of forming isolation layer of semiconductor device A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate... | 09/30/2008 |
| 7416948 | Trench FET with improved body to gate alignment A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductiv... | 08/26/2008 |
| 7393752 | Semiconductor devices and method of fabrication A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlyi... | 07/01/2008 |
| 7387942 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 06/17/2008 |
| 7384839 | SRAM cell with asymmetrical transistors for reduced leakage A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabricatio... | 06/10/2008 |
| 7364994 | Method for manufacturing a superjunction device with wide mesas A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewal... | 04/29/2008 |
| 7358149 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 04/15/2008 |
| 7351637 | Semiconductor transistors having reduced channel widths and methods of fabricating same A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a... | 04/01/2008 |
| 7348814 | Power-on reset circuit A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset... | 03/25/2008 |
| 7348225 | Structure and method of fabricating FINFET with buried channel A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first materi... | 03/25/2008 |
| 7341902 | Finfet/trigate stress-memorization method Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the sem... | 03/11/2008 |
| 7329618 | Ion implanting methods An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received ... | 02/12/2008 |
| 7316978 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 01/08/2008 |
| 7303967 | Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an... | 12/04/2007 |
| 7300848 | Semiconductor device having a recess gate for improved reliability A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain are... | 11/27/2007 |
| 7301203 | Superjunction semiconductor device In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the ... | 11/27/2007 |
| 7297581 | SRAM formation using shadow implantation A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant proce... | 11/20/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7291535 | Method and apparatus for fabricating semiconductor device A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating f... | 11/06/2007 |
| 7285465 | Method of manufacturing a SiC vertical MOSFET A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by... | 10/23/2007 |
| 7282426 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has ... | 10/16/2007 |
| 7279387 | Method for fabricating asymmetric semiconductor device A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in ... | 10/09/2007 |
| 7279711 | Ferroelectric liquid crystal and goggle type display devices The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode ... | 10/09/2007 |
| 7279430 | Process for fabricating a strained channel MOSFET device A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlyin... | 10/09/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7259427 | Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode ... | 08/21/2007 |
