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| Number | Title | Issue Date |
| 8084340 | Method of manufacturing semiconductor device and semiconductor device A method of manufacturing a semiconductor device whereby, even in cases where ions are implanted into a shallow region of a semiconductor substrate when a deep well is formed, the influence of the ions on a MOSFET can be removed, thereby eliminating the need for inc... | 12/27/2011 |
| 7981781 | Metal line of semiconductor device having a diffusion barrier and method for forming the same A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The di... | 07/19/2011 |
| 7927989 | Method for forming a transistor having gate dielectric protection and structure A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to ... | 04/19/2011 |
| 7829446 | Method for dividing wafer, method for manufacturing silicon devices, and method for manufacturing liquid ejecting heads A method for dividing a wafer into a plurality of chips is provided. The method includes providing recesses in a surface of the wafer at positions along boundaries between regions to become the individual chips, providing fragile portions having a predetermined widt... | 11/09/2010 |
| 7700468 | Semiconductor device and method of fabricating the same Provided are a semiconductor device and a method of fabricating the semiconductor device. In the method, a field oxide layer can be formed in a semiconductor substrate so as to define and active electrode including a gate oxide layer and a gate poly is formed in the... | 04/20/2010 |
| 7429519 | Method of forming isolation layer of semiconductor device A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate... | 09/30/2008 |
| 7419858 | Recessed-gate thin-film transistor with self-aligned lightly doped drain A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bott... | 09/02/2008 |
| 7416948 | Trench FET with improved body to gate alignment A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductiv... | 08/26/2008 |
| 7410891 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 08/12/2008 |
| 7399679 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the t... | 07/15/2008 |
| 7393766 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polys... | 07/01/2008 |
| 7387942 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 06/17/2008 |
| 7384861 | Strain modulation employing process techniques for CMOS technologies A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the ... | 06/10/2008 |
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat... | 04/29/2008 |
| 7358566 | Semiconductor device A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semi... | 04/15/2008 |
| 7335972 | Heterogeneously integrated microsystem-on-a-chip A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect struct... | 02/26/2008 |
| 7332388 | Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide forma... | 02/19/2008 |
| 7319377 | Method for making high-performance RF integrated circuits A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region.... | 01/15/2008 |
| 7316978 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 01/08/2008 |
| 7314794 | Low-cost high-performance planar back-gate CMOS A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-ga... | 01/01/2008 |
| 7314800 | Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat... | 01/01/2008 |
| 7312133 | Method of manufacturing semiconductor device A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into ... | 12/25/2007 |
| 7300848 | Semiconductor device having a recess gate for improved reliability A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain are... | 11/27/2007 |
| 7297582 | Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) ... | 11/20/2007 |
| 7294536 | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.... | 11/13/2007 |
| 7282415 | Method for making a semiconductor device with strain enhancement A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the co... | 10/16/2007 |
| 7279397 | Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively p... | 10/09/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7241671 | CMOS image sensor and method for fabricating the same A CMOS image sensor includes a first conductive type semiconductor substrate having an active region and a device isolation region, a device isolation film formed in the device isolation region of the semiconductor substrate, a second conductive type diffusion regio... | 07/10/2007 |
| 7226841 | Power MOSFET semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate of a first conductivity type, on which a semiconductor layer having a trench extending in the depth direction toward the semiconductor substrate is formed. A first region of the first conductivity type is for... | 06/05/2007 |
| 7226846 | Method of dry etching semiconductor substrate to reduce crystal defects in a trench A silicon oxide film (12) and a silicon nitride film (13) are sequentially formed over a silicon substrate (11) having a plane orientation (100). A trench (14) is formed with the patterned silicon nitride (13) as a mask. Argon is i... | 06/05/2007 |
| 7220661 | Method of manufacturing a Schottky barrier rectifier A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second do... | 05/22/2007 |
| 7217985 | Semiconductor device including a transistor having low threshold voltage and high breakdown voltage A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconducto... | 05/15/2007 |
| 7195977 | Method for fabricating a semiconductor device A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming gate lines on the field oxide regions and the... | 03/27/2007 |
| 7183206 | Fabrication of semiconductor devices Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked l... | 02/27/2007 |
| 7183183 | Method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall o... | 02/27/2007 |
| 7183193 | Integrated device technology using a buried power buss for major device and circuit advantages A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidiz... | 02/27/2007 |
| 7179748 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 02/20/2007 |
| 7176131 | Electronic component having at least one semiconductor chip and flip-chip contacts, and method for producing the same An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silico... | 02/13/2007 |
| 7176095 | Bi-modal halo implantation Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first... | 02/13/2007 |
