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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7507646 | Semiconductor devices and method of manufacturing them With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among ... | 03/24/2009 |
| 7410860 | Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick ... | 08/12/2008 |
| 7385246 | Depletable cathode low charge storage diode An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and... | 06/10/2008 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7172933 | Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate... | 02/06/2007 |
| 7078325 | Process for producing a doped semiconductor substrate A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and acc... | 07/18/2006 |
| 7078756 | Collarless trench DRAM device The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same. ... | 07/18/2006 |
| 7026650 | Multiple floating guard ring edge termination for silicon carbide devices Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on t... | 04/11/2006 |
| 7005334 | Zero threshold voltage pFET and method of making same A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent... | 02/28/2006 |
| 7005364 | Method for manufacturing semiconductor device The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern. The method for manufacturing a semiconductor device in... | 02/28/2006 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6897103 | MOS integrated circuit with reduced on resistance An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The islan... | 05/24/2005 |
| 6818534 | DRAM having improved leakage performance and method for making same A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises a buried-strap junction formed adjacent to the shallow trench isolation and above the collar oxide, and a... | 11/16/2004 |
| 6777758 | Semiconductor device P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50 | 08/17/2004 |
| 6670245 | Method for fabricating an ESD device The present invention provides a method for fabricating an ESD device. First, a substrate undergoes first implantation to form a first first-type well comprising an electrostatic discharge region. Next, second implantation is performed on the substrate an... | 12/30/2003 |
| 6635505 | Method of manufacturing an active matrix type semiconductor display device There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, diffe... | 10/21/2003 |
| 6621131 | Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and... | 09/16/2003 |
| 6583060 | Dual depth trench isolation A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structu... | 06/24/2003 |
| 6541359 | Optimized gate implants for reducing dopant effects during gate etching A method and apparatus thereof for fabricating an integrated circuit on a laminate having a gate electrode layer over a silicon dioxide layer. Detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material... | 04/01/2003 |
| 6482714 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a chann... | 11/19/2002 |
| 6433392 | Electrostatic discharge device and method The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collect... | 08/13/2002 |
| 6383850 | Semiconductor device and method of manufacturing the same In a region on the left hand of FIG. 1 with respect to the gate electrode (107), a first source region (103a), a body-potential drawing region (105) and a second source region (103b) are formed in this order along the vertical direction of this figure. Th... | 05/07/2002 |
| 6291323 | Method of fabrication of semiconductor structures by ion implantation The present invention relates to the formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. Ions of a P-type dopant are implanted into a semiconductor... | 09/18/2001 |
| 6232182 | Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region ... | 05/15/2001 |
| 6040237 | Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers and where the edge of the highe... | 03/21/2000 |
| 5773358 | Method of forming a field effect transistor and method of forming CMOS integrated circuitry Methods of forming field effect transistors. In one aspect, a method of forming a field effect transistor includes: a) providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a d... | 06/30/1998 |
| 5491768 | Optical waveguide employing modified gallium arsenide In an optical waveguide fabrication process, medium weight, relatively stable ions, such as oxygen ions, are implanted, preferably in a multiple-step, multiple-energy level process, into GaAs, InP or other like III-V materials and heterostructures and the... | 02/13/1996 |
| 5405792 | Method of manufacturing schottky barrier gate type fet The method of manufacturing the SB FET according to the present invention includes a first step of forming a refractory metal film on a semiconductor substrate, a second step of forming a first ion-implanted region within the semiconductor substrate, by a... | 04/11/1995 |
| 5314833 | Method of manufacturing GaAs metal semiconductor field effect transistor A method of manufacturing a GaAs field effect transistor comprises depositing a silicon thin film 202 on a semi-insulating semiconductor substrate 201, forming a first sensitive film 203 by a photolithography to define channel areas and ion-implanting n-t... | 05/24/1994 |
| 5126277 | Method of manufacturing a semiconductor device having a resistor After doping a conductive layer made of a semiconductive material with impurites, a conductive layer with a deep trap level is formed by low temperature annealing. For forming such a conductive layer with a deep level, lattice defects are introduced into ... | 06/30/1992 |
| 5036017 | Method of making asymmetrical field effect transistor A method of making a field effect transistor includes forming an active layer in a semiconductor substrate, forming a gate material on a portion of the surface as an ion implantation mask, implanting dopant ions to form a source region, depositing a first... | 07/30/1991 |
| 5030579 | Method of making an FET by ion implantation through a partially opaque implant mask Semiconductor processing techniques and devices are provided using a partially opaque ion implantation mask to control the profile of active layers in microwave and millimeter wave monolithic integrated circuits. An N+ layer can be implanted before or aft... | 07/09/1991 |
| 4532695 | Method of making self-aligned IGFET The IGFET is formed on a GaAs wafer which is coated with a layer of Si3 N4 and a SiO2 layer. The SiO2 is etched away in transistor areas, and ion implanting provides channel doping. A gate of refractory metal su... | 08/06/1985 |
| 4519127 | Method of manufacturing a MESFET by controlling implanted peak surface dopants A method of manufacturing a metal semiconductor field-effect transistor (MESFET) by controlling implanted peak surface dopants, is provided which comprises the steps of selectively ion-implanting an impurity in the surface of a semi-insulating substrate m... | 05/28/1985 |
| 4494997 | Ion implant mask and cap for gallium arsenide structures A mask and encapsulating layer suitable for use on gallium arsenide substrates is described incorporating a layer of germanium selenide which is photosensitive and may be exposed and developed to form a mask suitable for ion implantation and which may als... | 01/22/1985 |
| 4452646 | Method of making planar III-V compound device by ion implantation A planar process and new structure which leads to large scale integration capability by utilizing selective ion implantation into semi-insulating Gallium Arsenide substrates or any other compound semi-conducting material to yield isolated depletion enhanc... | 06/05/1984 |
| 4193182 | Passivated V-gate GaAs field-effect transistor and fabrication process therefor The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implanatation doping steps are used to form source, drain and channel regions in a semiconductor... | 03/18/1980 |
| 4116717 | Ion implanted eutectic gallium arsenide solar cell An improved gallium arsenide solar cell is provided by ion implanting both the top and bottom of a plural vertical PN junction eutectic gallium arsenide cell body to obtain an electrical drift field, with multiple ion implants progressively larger in dose... | 09/26/1978 |
