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| Number | Title | Issue Date |
| 8110487 | Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and... | 02/07/2012 |
| 8058158 | Hybrid semiconductor substrate including semiconductor-on-insulator region and method of making the same A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over th... | 11/15/2011 |
| 8058157 | FinFET structure with multiply stressed gate electrode A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and ... | 11/15/2011 |
| 7749875 | Method of manufacturing a semiconductor element and semiconductor element A method of manufacturing a semiconductor element. A dislocation region is formed between a first layer and a second layer, the dislocation region including a plurality of dislocations. First interstitials in the first layer are at least partially eliminated using t... | 07/06/2010 |
| 7700466 | Tunneling effect transistor with self-aligned gate In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from wi... | 04/20/2010 |
| 7659187 | Method of forming PN junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then anneal... | 02/09/2010 |
| 7601620 | Methods for fabricating nanocoils Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which... | 10/13/2009 |
| 7534705 | Method of manufacturing a semiconductor device An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser l... | 05/19/2009 |
| 7442614 | Silicon on insulator devices having body-tied-to-source and methods of making Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer... | 10/28/2008 |
| 7442586 | SOI substrate and SOI device, and method for forming the same An improved semiconductor-on-insulator (SOI) substrate is provided, which has a substantially planar upper surface and comprises at least first and second patterned buried insulator layers. Specifically, the first patterned buried insulator layer has a first thickne... | 10/28/2008 |
| 7442585 | MOSFET with laterally graded channel region and method for manufacturing same The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel regio... | 10/28/2008 |
| 7427538 | Semiconductor on insulator apparatus and method A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer ... | 09/23/2008 |
| 7393724 | Reduced dielectric breakdown/leakage semiconductor device and a method of manufacturing the same, integrated circuit, electro-optical device, and electric apparatus Aspects of the invention provide a method, in a semiconductor device, such as a thin film transistor, a technology capable of preventing or reducing the electric field concentration at the edge section of the semiconductor film to enhance the reliability. The method... | 07/01/2008 |
| 7365369 | Nitride semiconductor device A nitride semiconductor device used chiefly as an LD and an LED element. In order to improve the output and to decrease Vf, the device is given either a three-layer structure in which a nitride semiconductor layer doped with n-type impurities serving as an n-type co... | 04/29/2008 |
| 7362784 | Laser irradiation method, laser irradiation apparatus, and semiconductor device An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of th... | 04/22/2008 |
| 7361577 | Method of manufacturing semiconductor device In a step of doping a silicon-based semiconductor film as a TFT active layer such as channel doping or the like, a protective film is formed by a CVD method as a pretreatment so as to prevent the silicon-based semiconductor film from being contaminated and etched. H... | 04/22/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7358511 | Plasma doping method and plasma doping apparatus A plasma doping method, even though a plasma doping treatment is repeated, can make a dose from a film to a silicon substrate uniform for each time. The method includes preparing a vacuum chamber having a film containing an impurity formed on an inner wall thereof s... | 04/15/2008 |
| 7352025 | Semiconductor memory device with increased node capacitance An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without ... | 04/01/2008 |
| 7348227 | Semiconductor device and manufacturing method thereof A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a ... | 03/25/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7335543 | MOS device for high voltage operation and method of manufacture A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is ove... | 02/26/2008 |
| 7332412 | Structure of strained silicon on insulator and method of manufacturing the same Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO | 02/19/2008 |
| 7329594 | Method of manufacturing a semiconductor device An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser l... | 02/12/2008 |
| 7326628 | Thin layer transfer method utilizing co-implantation to reduce blister formation and to surface roughness A method for producing a semiconductor structure by conducting controlled co-implanting of at least first and second different atomic species into a donor substrate to create an embrittlement zone which defines a thin layer of donor material to be transferred. Impla... | 02/05/2008 |
| 7307467 | Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at le... | 12/11/2007 |
| 7294535 | Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A heat treatment is carried out for an amorphous semiconductor thin film, to thereby obtain a crystalline semiconductor thin fil... | 11/13/2007 |
| 7291521 | Self correcting suppression of threshold voltage variation in fully depleted transistors A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first... | 11/06/2007 |
| 7291568 | Method for fabricating a nitrided silicon-oxide gate dielectric A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitr... | 11/06/2007 |
| 7285495 | Methods for thermally treating a semiconductor layer A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer l... | 10/23/2007 |
| 7282449 | Thermal treatment of a semiconductor layer A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth ... | 10/16/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7276428 | Methods for forming a semiconductor structure Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species ... | 10/02/2007 |
| 7268029 | Method of fabricating CMOS transistor that prevents gate thinning Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implante... | 09/11/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7264996 | Method for separating wafers bonded together to form a stacked structure This invention relates to a method for separating at least two wafers (1, 2) bonded together to form a stacked structure. At least one bending force is applied to all or part of the stacked structure to separate the stacked structure into two parts along a re... | 09/04/2007 |
| 7265435 | Method for implanting atomic species through an uneven surface of a semiconductor layer A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes impla... | 09/04/2007 |
| 7253049 | Method for fabricating dual work function metal gates A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method ... | 08/07/2007 |
| 7235469 | Semiconductor device and method for manufacturing the same A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a ge... | 06/26/2007 |
| 7232739 | Multifunctional metallic bonding Methods are provided for producing a transfer layer of a semiconductor material on a final substrate. In some embodiments, the transfer layer is produced on the final substrate by forming a layer of semiconductor material on an initial support, assembling that layer... | 06/19/2007 |
