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| Number | Title | Issue Date |
| 7410890 | Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams. ... | 08/12/2008 |
| 7396745 | Formation of ultra-shallow junctions by gas-cluster ion irradiation Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams. ... | 07/08/2008 |
| 7397048 | Technique for boron implantation A technique for boron implantation is disclosed. In one particular exemplary embodiment, the technique may be realized by an apparatus for boron implantation. The apparatus may comprise a reaction chamber. The apparatus may also comprise a source of pentaborane coup... | 07/08/2008 |
| 7381607 | Method of forming a spiral inductor in a semiconductor substrate An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in on... | 06/03/2008 |
| 7344963 | Method of reducing charging damage to integrated circuits during semiconductor manufacturing A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein t... | 03/18/2008 |
| 7294590 | System and method for removing charges with enhanced efficiency Method and apparatus for removing and neutralizing charges. The method includes loading a structure into a chamber. The structure includes a first surface and a plurality of charges away from the first surface. Additionally, the method includes supplying a first ion... | 11/13/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7205250 | Plasma processing method and apparatus A Plasma processing method and apparatus exhibit excellent characteristics of reducing the amount of electric charge on a plasma-processed processing-object substrate and of preventing plasma damage and dielectric breakdown. Before the processing-object substrate is... | 04/17/2007 |
| 7172981 | Semiconductor integrated circuit device manufacturing method including static charge elimination A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor sub... | 02/06/2007 |
| 7170147 | Dissipative isolation frames for active microelectronic devices, and methods of making such dissipative isolation frames Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in... | 01/30/2007 |
| 7138322 | Semiconductor device and fabrication method therefor An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and ar... | 11/21/2006 |
| 7094670 | Plasma immersion ion implantation process A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersi... | 08/22/2006 |
| 7071067 | Fabrication of integrated devices using nitrogen implantation A process is provided for forming an isolating nitride film to isolate gate polysilicon of a gate structure. Specifically, the process comprises providing a channel region defined by a source and drain region of a semiconductor substrate having a gate structure comp... | 07/04/2006 |
| 7038203 | Method for observing high-altitude neutral air and device for observing high-altitude neutral air Ion particles are discharged so as to be influenced by a magnetic field originated from the earth, and collided with high-altitude neutral air to generate high velocity neutral particles through charge exchange. The high velocity neutral particles are analyzed. The ... | 05/02/2006 |
| 6964917 | Semi-insulating silicon carbide produced by Neutron transmutation doping A method is disclosed for producing highly uniform semi-insulating characteristics in single crystal silicon carbide for semiconductor applications. The method includes irradiating a silicon carbide single crystal having net p-type doping and deep levels with neutro... | 11/15/2005 |
| 6841460 | Anti-type dosage as LDD implant A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. Th... | 01/11/2005 |
| 6825133 | Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively c... | 11/30/2004 |
| 6803275 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to dec... | 10/12/2004 |
| 6764917 | SOI device with different silicon thicknesses A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thicknes... | 07/20/2004 |
| 6756257 | Patterned SOI regions on semiconductor chips A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be sui... | 06/29/2004 |
| 6693012 | Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form ... | 02/17/2004 |
| 6620666 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conduc... | 09/16/2003 |
| 6610614 | Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containin... | 08/26/2003 |
| 6569691 | Measurement of different mobile ion concentrations in the oxide layer of a semiconductor wafer A method and apparatus for measuring the concentration of different mobile ions in the oxide layer of a semiconductor wafer from the contact potential shift caused by different ions drifting across the oxide that includes depositing charge (e.g., using a ... | 05/27/2003 |
| 6537891 | Silicon on insulator DRAM process utilizing both fully and partially depleted devices This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices ar... | 03/25/2003 |
| 6531367 | Method for forming ultra-shallow junction by boron plasma doping A method for forming an ultra-shallow junction by boron plasma doping is disclosed. A substrate is placed in a pulse type electric field. A flowing carrying gas drives boron ions in a channel above the substrate, and then a negative pulse type voltage is ... | 03/11/2003 |
| 6451674 | Method for introducing impurity into a semiconductor substrate without negative charge buildup phenomenon A method for introducing an impurity includes the steps of: introducing an impurity having charges into a target to be processed, such as a semiconductor substrate and a film formed on a substrate; and supplying electrons from a filament into the target t... | 09/17/2002 |
| 6403454 | Silicon semiconductor devices with δ-doped layers We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×10 | 06/11/2002 |
| 6372590 | Method for making transistor having reduced series resistance A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection w... | 04/16/2002 |
| 6300208 | Methods for annealing an integrated device using a radiant energy absorber layer The invented method can be used to melt and recrystallize the source and drain regions of an integrated transistor device(s) using a laser, for example. The invented method counteracts shadowing and interference effects caused by the presence of the gate ... | 10/09/2001 |
| 6287881 | Semiconductor device with low parasitic capacitance A method of fabricating a semiconductor device having active components grown on a substrate, involves providing a semiconductor substrate on which the active components are grown, and doping the semiconductor substrate to render it non conductive and the... | 09/11/2001 |
| 6284580 | Method for manufacturing a MOS transistor having multi-layered gate oxide In a pretreatment process, a silicon oxide film (13) with nitrogen content is formed on a semiconductor substrate (10). In a segregation process executing heat treatment in an inert gas atmosphere, a silicon nitride layer (14) segregates out at the interf... | 09/04/2001 |
| 6281053 | Thin film transistor with reduced hydrogen passivation process time A thin film field effect transistor includes source and drain regions, an active region sandwiched by the source and drain semiconductor regions. A gate insulating film is provided to cover the source and drain regions and the active region, and a semicon... | 08/28/2001 |
| 6261874 | Fast recovery diode and method for its manufacture A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recover... | 07/17/2001 |
| 6261889 | Manufacturing method of semiconductor device After a source-drain region is formed, fluorine 24 is ion-implanted into the entire surface of a substrate and thereafter a heat treatment is conducted, for example, at 600 to 800° C. Through this heat treatment, the dangling binds and the Si--H bonds in... | 07/17/2001 |
| 6251757 | Formation of highly activated shallow abrupt junction by thermal budget engineering In a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predeterm... | 06/26/2001 |
| 6248649 | Controlled cleavage process and device for patterned films using patterned implants A technique for forming a film of material from a donor substrate. The technique has a step of introducing energetic particles in a selected patterned manner through a surface of a donor substrate having devices to a selected depth underneath the surface,... | 06/19/2001 |
| 6235607 | Method for establishing component isolation regions in SOI semiconductor device A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and below the buried oxide layer. The implanted species interac... | 05/22/2001 |
| 6228720 | Method for making insulated-gate semiconductor element An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of ... | 05/08/2001 |
