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| Number | Title | Issue Date |
| 8168519 | Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfa... | 05/01/2012 |
| 8143150 | Method of fabricating semiconductor device and electronic system A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the wel... | 03/27/2012 |
| 8124508 | Method for low temperature ion implantation Techniques for low temperature ion implantation are provided to improve the throughput. During a low temperature ion implantation, an implant process may be started before the substrate temperature is decreased to be about to a prescribed implant temperature by a co... | 02/28/2012 |
| 8105927 | Method for manufacturing ion implantation mask, and method for manufacturing silicon carbide semiconductor device A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibitin... | 01/31/2012 |
| 8058156 | Plasma immersion ion implantation reactor having multiple ion shower grids A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion ge... | 11/15/2011 |
| 8053341 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern ha... | 11/08/2011 |
| 8053340 | Method for fabricating semiconductor devices with reduced junction diffusion A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source... | 11/08/2011 |
| 8048788 | Method for treating non-planar structures using gas cluster ion beam processing A method for treating a structure is described. One embodiment includes forming a structure on a substrate, wherein the structure has a plurality of surfaces including one or more first surfaces lying substantially parallel to a first plane parallel with said substr... | 11/01/2011 |
| 8039374 | Method for low temperature ion implantation Techniques for low temperature ion implantation are provided to improve throughput. Specifically, the pressure of the backside gas may temporarily, continually or continuously increase before the starting of the implant process, such that the wafer may be quickly co... | 10/18/2011 |
| 8003502 | Semiconductor device and fabrication method A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second ... | 08/23/2011 |
| 7977222 | Manufacturing method of semiconductor device Doping with suppressed filament deterioration can be performed even in the case of doping in various conditions with an ion doping apparatus having a filament. After ion doping is completed, supply of a material gas is stopped and hydrogen or a rare gas is kept to b... | 07/12/2011 |
| 7972946 | Plasma treatment method and plasma treatment device Provided are a plasma treatment method and a plasma treatment device capable of forming a silicon nitride film having high compressive stress. In the plasma treatment method for depositing the silicon nitride film on a process target substrate by use of plasma of ra... | 07/05/2011 |
| 7968440 | Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering Described herein are processing conditions, techniques, and methods for preparation of ultra-shallow semiconductor junctions. Methods described herein utilize semiconductor surface processing or modification to limit the extent of dopant diffusion under annealing co... | 06/28/2011 |
| 7968439 | Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfa... | 06/28/2011 |
| 7960264 | Lithography for printing constant line width features An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is de... | 06/14/2011 |
| 7935618 | Sputtering-less ultra-low energy ion implantation Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided. ... | 05/03/2011 |
| 7935619 | Polarity dependent switch for resistive sense memory Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecti... | 05/03/2011 |
| 7927987 | Method of reducing channeling of ion implants using a sacrificial scattering layer Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacri... | 04/19/2011 |
| 7927988 | Method of fabricating semiconductor device Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating proc... | 04/19/2011 |
| 7910466 | Method of manufacturing high-voltage semiconductor device and low-voltage semiconductor device A high-voltage semiconductor device and a method for making the same are provided. A high-voltage semiconductor device and a low-voltage semiconductor device are formed in a single substrate, a photolithography process that is required to form a high-voltage well re... | 03/22/2011 |
| 7879701 | Manufacturing method of semiconductor device Doping with suppressed filament deterioration can be performed even in the case of doping in various conditions with an ion doping apparatus having a filament. After ion doping is completed, supply of a material gas is stopped and hydrogen or a rare gas is kept to b... | 02/01/2011 |
| 7879702 | Method for manufacturing a semiconductor device including a memory cell array area and peripheral circuit area A method for manufacturing a semiconductor device includes the consecutive steps of selectively implanting first-conductivity-type impurities into a silicon substrate in a memory cell array area to form first source/drain regions, heat treating to diffuse the impuri... | 02/01/2011 |
| 7863169 | Lithography for printing constant line width features An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is de... | 01/04/2011 |
| 7833888 | Integrated circuit system employing grain size enlargement An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a do pant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the... | 11/16/2010 |
| 7825015 | Method for implanting ions in semiconductor device The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to ent... | 11/02/2010 |
| 7781315 | Finfet field effect transistor insulated from the substrate A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate throug... | 08/24/2010 |
| 7767561 | Plasma immersion ion implantation reactor having an ion shower grid A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lo... | 08/03/2010 |
| 7763530 | Doping of particulate semiconductor materials The invention relates to a method of doping semiconductor material. Essentially, the method comprises mixing a quantity of particulate semiconductor material with an ionic salt or a preparation of ionic salts. Preferably, the particulate semiconductor material compr... | 07/27/2010 |
| 7754588 | Method to improve a copper/dielectric interface in semiconductor devices Embodiments of methods for improving a copper/dielectric interface in semiconductor devices are generally described herein. Other embodiments may be described and claimed. ... | 07/13/2010 |
| 7749874 | Deep implant self-aligned to polysilicon gate A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment bet... | 07/06/2010 |
| 7727866 | Use of chained implants in solar cells The manufacture of solar cells is simplified and cost reduced through by performing successive ion implants, without an intervening thermal cycle. In addition to reducing process time, the use of chained ion implantations may also improve the performance of the sola... | 06/01/2010 |
| 7709363 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device including a first conductive type impurity region formed by introducing a first conductive type impurities in a first region of a semiconductor region and heating the first region, a second conductive type impurity r... | 05/04/2010 |
| 7709364 | Method and apparatus for low temperature ion implantation Techniques for low temperature ion implantation are disclosed. After a wafer is cooled to a temperature lower than a temperature of an environment outside of a chamber where the wafer is implanted, the cooled wafer is implanted by projecting an ion beam on the coole... | 05/04/2010 |
| RE41181 | Manufacturing method of semiconductor device A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradia... | 03/30/2010 |
| 7682954 | Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method An impurity region having a box-shaped impurity profile is formed. An impurity introducing method includes a step of introducing a desired impurity into a surface of a solid base body, and a step of radiating plasma to a surface of the solid base body after t... | 03/23/2010 |
| 7670936 | Nitridation of gate oxide by laser processing A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed ove... | 03/02/2010 |
| 7659186 | Method of manufacturing CMOS image sensor A method for manufacturing the CMOS image sensor comprising forming an epitaxial layer provided with a plurality of photo diodes on a semiconductor substrate, coating a first photo resist on the epitaxial layer and performing a patterning process on the first photo ... | 02/09/2010 |
| 7655545 | Image sensor and method of fabricating the same An image sensor includes a first photodiode formed in a semiconductor substrate at a depth reachable by red light, a second photodiode disposed on or over the first photodiode in the semiconductor substrate at a depth reachable by blue light, a third photodiode disp... | 02/02/2010 |
| 7645690 | Method for producing an integrated circuit having semiconductor zones with a steep doping profile An integrated circuit and method, producing semiconductor zones with a steep doping profile is disclosed. In one embodiment, dopants are implanted in a region corresponding to the semiconductor zone to be formed and which has at least one topology process. During th... | 01/12/2010 |
| 7629238 | Device isolation structure of a semiconductor device and method of forming the same Disclosed are an isolation structure and a method for forming the same. The present isolation structure includes a substrate having a first semiconductor layer having a first lattice parameter, a second semiconductor layer having a second lattice parameter larger th... | 12/08/2009 |