Class 438/511 - Ordering or disordering

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making semiconductor regions of the substrate
No. of patents: 34
Last issue date: 02/28/2012

Number	Title	Issue Date
8124506	USJ techniques with helium-treated substrates A method of using helium to create ultra shallow junctions is disclosed. A pre-implantation amorphization using helium has significant advantages. For example, it has been shown that dopants will penetrate the substrate only to the amorphous-crystalline interface, a...	02/28/2012
7622372	Method for shallow dopant distribution Vacancies and dopant ions are introduced near the surface of a semiconductor layer structure. Implanted dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow j...	11/24/2009
7517776	Method for controlling dislocation positions in silicon germanium buffer layers A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on th...	04/14/2009
7468313	Engineering strain in thick strained-SOI substrates A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is anneale...	12/23/2008
7282427	Method of implanting a substrate and an ion implanter for performing the method An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the...	10/16/2007
7276431	Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does...	10/02/2007
7268065	Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se...	09/11/2007
7161220	High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for ...	01/09/2007
7157356	Method for forming a notched gate insulator for advanced MIS semiconductor devices and devices thus obtained Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back...	01/02/2007
7110428	Vertical cavity surface emitting laser A vertical cavity surface emitting laser, including an active region, an electrical contact for injecting current into the active region in order to generate photons, and an aperture between the active region and the contact for restricting current flow into the act...	09/19/2006
6998303	Manufacture method for semiconductor device with patterned film of ZrO or the like An insulating film made of zirconia or hafnia is formed on the surface of a semiconductor substrate. A partial surface area of the insulating film is covered with a mask pattern. By using the mask pattern as a mask, ions are implanted into a region of the insulating...	02/14/2006
6949399	Method of reducing contamination-induced process variations during ion implantation When changing a dopant species in an implantation tool, typically a clean process is performed to reduce cross-contamination, which is considered a major issue in implant cycles applied in advanced CMOS processes. Especially, the employment of an implanter previousl...	09/27/2005
6944197	Low crosstalk optical gain medium and method for forming same An optical gain medium, and a method for forming the same, is provided that exhibits lower wavelength crosstalk when configured as an optical amplifier than prior art optical gain media. The optical gain medium of the present invention includes a buried heterostruct...	09/13/2005
6936526	Method of disordering quantum well heterostructures A method of disordering a quantum well heterostructure, including the step of irradiating the heterostructure with a particle beam, wherein the energy of the beam is such that the beam creates a substantially constant distribution of defects within the heterostructu...	08/30/2005
6908836	Method of implanting a substrate and an ion implanter for performing the method An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the...	06/21/2005
6906800	Polarimeter using quantum well stacks separated by gratings Quantum well stacks are used in combination with linear gratings to determine the degree of polarization of incident light in terms of Stokes parameters. Interference from multiple reflections, diffractions and transmissions of the light propagating from and through...	06/14/2005
6855592	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is disclosed, in which characteristics of the semiconductor device and an operation speed are improved. In forming sidewall spacers at both sides of a gate electrode, a semiconductor substrates is partially removed a...	02/15/2005
6808970	Semiconductor device having an improved strained surface layer and method of forming a strained surface layer in a semiconductor device A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xen...	10/26/2004
6544899	Process for manufacturing silicon epitaxial wafer There is provided a process for manufacturing a silicon epitaxial wafer capable of manufacturing an epitaxial wafer, which exerts a stable IG capability without being affected by a thermal history of a substrate for epitaxial growth and has the IG capabil...	04/08/2003
6544888	Advanced contact integration scheme for deep-sub-150 nm devices An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes wit...	04/08/2003
6426519	Epitaxial growth substrate and a method for producing the same Strip-shaped ditches are formed on a sapphire substrate as a base material. Then, the sapphire substrate is set into a CVD chamber, and an Alx Gay Inz N (x+y+z=1,x>0,y,zࣙ0)film is epitaxially grown on the sapphire substr...	07/30/2002
6410413	Semiconductor device with transparent link area for silicide applications and fabrication thereof Useful to inhibit reverse engineering, semiconductor devices and methods therefore include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heav...	06/25/2002
6403454	Silicon semiconductor devices with δ-doped layers We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×10	06/11/2002
6391695	Double-gate transistor formed in a thermal process A method for forming a double-gate SOI MOS transistor with a back gate formed by a laser thermal process is described. In this method, a back gate is formed in a semiconductor substrate and is subsequently amorphized by implanting an amorphization species...	05/21/2002
6362083	Method for fabricating locally reinforced metallic microfeature A method for fabricating a locally reinforced metallic microfeature on a substrate provided preferably with an electrical contacting or a driving circuit, and on an organic, patterned sacrificial layer, which is removed after the metallic microfeature is ...	03/26/2002
6358807	Bipolar semiconductor device and method of forming same having reduced transient enhanced diffusion A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 10...	03/19/2002
6284630	Method for fabrication of abrupt drain and source extensions for a field effect transistor Drain and source extensions that are abrupt and shallow and that have high concentration of dopant are fabricated for a field effect transistor, using a laser thermal process. A drain amorphous region is formed by implanting a neutral species into a drain...	09/04/2001
6255122	Amorphous dielectric capacitors on silicon High-capacity capacitors and gate insulators exhibiting moderately high dielectric constants with surprisingly low leakage using amorphous or low temperature films of perovskite type oxides including a titanate system material such as barium titanate, str...	07/03/2001
6232208	Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to fo...	05/15/2001
6168981	Method and apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in th...	01/02/2001
5993538	Method of forming single-crystalline thin film using beam irradiating method In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reactio...	11/30/1999
5238868	Bandgap tuning of semiconductor quantum well structures A method of selectively tuning the bandedge of a semi-conductor heterostructure includes forming a disordered region which is spatially separated from a quantum well active region, and subsequently annealing the heterostructure so that vacancies/defects i...	08/24/1993
5182229	Method for diffusing an n type impurity from a solid phase source into a III-V compound semiconductor A method for diffusing n type impurities from a solid phase source into a III-V compound semiconductor includes depositing an amorphous or polycrystalline selenium or sulfur film on the III-V compound semiconductor and diffusing selenium or sulfur from th...	01/26/1993
4671830	Method of controlling the modeling of the well energy band profile by interdiffusion The method of controlling the modeling of the well energy band profile by interdiffusion comprises at least one thin disordering component layer contiguous with a surface of the quantum well layer and including a high content of a disordering component th...	06/09/1987

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Class 438/511 - Ordering or disordering