Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8173526 | Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional... | 05/08/2012 |
| 8163635 | Manufacturing method of semiconductor device A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method furt... | 04/24/2012 |
| 8138070 | Methods of using a set of silicon nanoparticle fluids to control in situ a set of dopant diffusion profiles A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink... | 03/20/2012 |
| 8105924 | Deep trench based far subcollector reachthrough A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semi... | 01/31/2012 |
| 8105923 | Sintered semiconductor material The invention relates to a method for forming a semiconductor material obtained by sintering powders and to a semiconductor material. The method comprises a compression and heat treatment stage such that one part of the powder is melted or becomes viscous. The mater... | 01/31/2012 |
| 8084338 | Semiconductor device and manufacturing method thereof The depletion of a gate electrode (103) is suppressed in such a way that impurities are introduced into the gate electrode that is formed on a semiconductor substrate (101), with a gate insulating film (102) interposed between the gate electrode... | 12/27/2011 |
| 8076225 | Solid-state image capturing device, manufacturing method for the same and electronic information device A method for manufacturing a solid-state image capturing device according to the present invention, in which from a plurality of light receiving sections for photoelectrically converting incident light into signal electric charge, the signal electric charge is read ... | 12/13/2011 |
| 8076226 | Apparatus for annealing, method for annealing, and method for manufacturing a semiconductor device An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a ... | 12/13/2011 |
| 8043946 | Mixture for doping semiconductors A doping mixture for coating semiconductor substrates which are then subjected to a high temperature treatment to form a doped layer includes at least one p- or n-dopant, water and a mixture of two or more surfactants. At least one of the surfactants is nonionic. Al... | 10/25/2011 |
| 7919400 | Methods for doping nanostructured materials and nanostructured thin films A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to ... | 04/05/2011 |
| 7906416 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom... | 03/15/2011 |
| 7846822 | Methods for controlling dopant concentration and activation in semiconductor structures The present invention provides methods for fabricating semiconductor structures and devices, particularly ultra-shallow doped semiconductor structures exhibiting low electrical resistance. Methods of the present invention use modification of the composition of semic... | 12/07/2010 |
| 7833886 | Method of producing a semiconductor element in a substrate A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amo... | 11/16/2010 |
| 7820532 | Methods for simultaneously forming doped regions having different conductivity-determining type element profiles Method for simultaneously forming doped regions having different conductivity-determining type elements profiles are provided. In one exemplary embodiment, a method comprises the steps of diffusing first conductivity-determining type elements into a first region of ... | 10/26/2010 |
| 7816239 | Technique for manufacturing a solar cell Techniques for manufacturing solar cells are disclosed. In one particular exemplary embodiment, the technique may comprise disposing a mask upstream of the solar cell, the mask comprising a plurality of filaments spaced apart from one another to define at least one ... | 10/19/2010 |
| 7795119 | Flash anneal for a PAI, NiSi process A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impu... | 09/14/2010 |
| 7790585 | Antiferromagnetic half-metallic semiconductor and manufacturing method therefor An antiferromagnetic half-metallic semiconductor of the present invention is manufactured by adding to a semiconductor two or more types of magnetic elements including a magnetic element with a d-electron number of less than five and a magnetic element with a d-elec... | 09/07/2010 |
| 7776725 | Anti-halo compensation An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length. The method includes doping a short channel device and a long channel device with a first dopant, and doping the short channel devi... | 08/17/2010 |
| 7776727 | Methods of emitter formation in solar cells Embodiments of the invention contemplate high efficiency emitters in solar cells and novel methods for forming the same. One embodiment of the improved emitter structure, called a high-low type emitter, optimizes the solar cell performance by equally providing low c... | 08/17/2010 |
| 7776726 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first im... | 08/17/2010 |
| 7737009 | Method of implanting a non-dopant atom into a semiconductor device A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modif... | 06/15/2010 |
| 7727865 | Method for controlling conductivity of GaOsingle crystal To provide a method of controlling a conductivity of a Ga2O3 system single crystal with which a conductive property of a β-Ga2O3 system single crystal can be efficiently controlled. The light emitting element inclu... | 06/01/2010 |
| 7713852 | Methods for forming field effect transistors and EPI-substrate A semiconductor method includes thermally treating at least a portion of a substrate so as to generate a plurality of vacancies in a region at a depth substantially near to a surface of the substrate. The substrate is then quenched so as to substantially maintain th... | 05/11/2010 |
| 7709361 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device includes forming an impurity diffusion layer in a surface of a semiconductor substrate, wherein the forming the impurity diffusion layer comprises irradiating material including M1x M2y ... | 05/04/2010 |
| 7691734 | Deep trench based far subcollector reachthrough A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semi... | 04/06/2010 |
| 7687383 | Methods of depositing electrically active doped crystalline Si-containing films Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including cryst... | 03/30/2010 |
| 7674695 | Wafer cleaning system An electromegasonic wafer cleaning system is disclosed that is extremely important, if not essential, in the fabrication of advanced microelectronic devices having a line width or feature size of from 0.05 to 0.10 micron. A unique synergistic combination is provided... | 03/09/2010 |
| 7648896 | Deposited semiconductor structure to minimize n-type dopant diffusion and method of making In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thic... | 01/19/2010 |
| 7589004 | Method for implantation of high dopant concentrations in wide band gap materials A method that combines alternate low/medium ion dose implantation with rapid thermal annealing at relatively low temperatures. At least one dopant is implanted in one of a single crystal and an epitaxial film of the wide band gap compound by a plurality of implantat... | 09/15/2009 |
| 7575986 | Gate interface relaxation anneal method for wafer processing with post-implant dynamic surface annealing Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting... | 08/18/2009 |
| 7569463 | Method of thermal processing structures formed on a substrate The present invention generally describes one or more apparatuses and various methods that are used to perform an annealing process on desired regions of a substrate. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferential... | 08/04/2009 |
| 7521342 | Semiconductor structure with high-voltage sustaining capability and fabrication method of the same A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to th... | 04/21/2009 |
| 7504326 | Use of scanning theme implanters and annealers for selective implantation and annealing A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ... | 03/17/2009 |
| 7494904 | Plasma-assisted doping Methods and apparatus are provided for igniting, modulating, and sustaining a plasma for various doping processes. In one embodiment, a substrate (250) can be doped by forming a plasma (610) in a cavity (285) by subjecting a gas to an amount of ... | 02/24/2009 |
| 7494905 | Method for preparing a source material including forming a paste for ion implantation The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110 | 02/24/2009 |
| 7491629 | Method for producing an n-doped field stop zone in a semiconductor body and semiconductor component having a field stop zone A method for producing an n-doped field stop zone in a semiconductor body. The method includes carrying out a diffusion process for the indiffusion of sulfur, hydrogen or selenium proceeding from one side into the semiconductor body in order to produce a first n-dop... | 02/17/2009 |
| 7491630 | Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles... | 02/17/2009 |
| 7442630 | Method for fabricating forward and reverse blocking devices A power device includes a gate electrode, a source electrode, and a drain electrode provided within an active region of a semiconductor substrate of first conductivity type. A vertical diffusion region of second conductivity is provided at a periphery the active reg... | 10/28/2008 |
| 7442640 | Semiconductor device manufacturing methods Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting... | 10/28/2008 |
| 7432178 | Bit line implant A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A ... | 10/07/2008 |
