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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8067301 | Image sensor and method for forming the same A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A... | 11/29/2011 |
| 7935616 | Dynamic p-n junction growth Methods of fabricating semiconductor p-n junctions and semiconductor devices containing p-n junctions are disclosed in which the p-n junctions contain concentration profiles for the p-type and n-type dopants that are controllable and independent of a dopant diffusio... | 05/03/2011 |
| 7858503 | Ion implanted substrate having capping layer and method In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer is deposited on the ion implanted region. The substrate is annealed to volatize at le... | 12/28/2010 |
| 7611975 | Method of implanting a substrate and an ion implanter for performing the method An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the... | 11/03/2009 |
| 7442657 | Producing stress-relaxed crystalline layer on a substrate A stress relaxed monocrystalline layer structure is made on a nonlattice matched substrate by first applying to the substrate epitaxially a monocrystalline layer structure comprising at least one layer, the monocrystalline layer structure forming with the substrate ... | 10/28/2008 |
| 7358127 | Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of t... | 04/15/2008 |
| 7354844 | Method for manufacturing SOI substrate The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness. The object is met by providing a method for manufacturing an SOI substrate comprising the... | 04/08/2008 |
| 7348231 | Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substr... | 03/25/2008 |
| 7344933 | Method of forming device having a raised extension region A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate... | 03/18/2008 |
| 7341929 | Method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer... | 03/11/2008 |
| 7309634 | Non-volatile semiconductor memory devices using prominences and trenches A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned w... | 12/18/2007 |
| 7288430 | Method of fabricating heteroepitaxial microstructures An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microst... | 10/30/2007 |
| 7282416 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 10/16/2007 |
| 7276421 | Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor ... | 10/02/2007 |
| 7268646 | Temperature controlled MEMS resonator and method for controlling resonator frequency There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and/or controlling microelectromechanical reso... | 09/11/2007 |
| 7265029 | Fabrication of substrates with a useful layer of monocrystalline semiconductor material Methods for fabricating a semiconductor substrate. In an embodiment, the technique includes providing an intermediate support, providing a nucleation layer, and providing at least one bonding layer between the intermediate support and the nucleation layer to improve... | 09/04/2007 |
| 7262113 | Methods for transferring a useful layer of silicon carbide to a receiving substrate Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the invention relates to a method for recycling of a silicon carbide source substrate by removal of the excess zone followed by a finishing step to p... | 08/28/2007 |
| 7253072 | Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405... | 08/07/2007 |
| 7238598 | Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element A method for forming a semiconductor substrate that can be dismantled, comprising the following steps: introduction of gaseous species in the substrate according to conditions enabling the constitution of an embrittled layer by the presence in said layer of micro-ca... | 07/03/2007 |
| 7238622 | Wafer bonded virtual substrate and method for forming the same A method of forming a virtual substrate comprised of an optoelectronic device substrate and handle substrate comprises the steps of initiating bonding of the device substrate to the handle substrate, improving or increasing the mechanical strength of the device and ... | 07/03/2007 |
| 7235462 | Methods for fabricating a substrate A method is provided for fabricating a substrate for optics, electronics, or opto-electronics. This method includes the steps of implanting atomic species into a face of a source substrate to form a weakened zone therein corresponding to the depth of penetration of ... | 06/26/2007 |
| 7221038 | Method of fabricating substrates and substrates obtained by this method Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous ... | 05/22/2007 |
| 7208392 | Creation of an electrically conducting bonding between two semi-conductor elements A method of creating an electrically conducting bonding between a face of a first semiconductor element and a face of a second semiconductor element using heat treatment. The method applies the faces one against the other with the placing between them of at least on... | 04/24/2007 |
| 7195986 | Microfluidic device with controlled substrate conductivity A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the mi... | 03/27/2007 |
| 7192844 | Glass-based SOI structures Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20... | 03/20/2007 |
| 7176528 | Glass-based SOI structures Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20... | 02/13/2007 |
| 7176102 | Method for producing SOI wafer and SOI wafer A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the m... | 02/13/2007 |
| 7139193 | Non-volatile memory with two adjacent memory cells sharing same word line A nonvolatile semiconductor memory device having a small layout size includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes a plurality of element isolation regions. Ea... | 11/21/2006 |
| 7118929 | Process for producing an epitaxial layer of gallium nitride The present invention relates to a process for producing an epitaxial layer of gallium nitride (GaN) as well as to the epitaxial layers of gallium nitride (GaN) which can be obtained by said process. Such a process makes it possible to obtain gallium nitride layers ... | 10/10/2006 |
| 7115451 | Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor subs... | 10/03/2006 |
| 7091130 | Method of forming a nanocluster charge storage device A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-fo... | 08/15/2006 |
| 7068125 | Temperature controlled MEMS resonator and method for controlling resonator frequency There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and/or controlling microelectromechanical reso... | 06/27/2006 |
| 7064414 | Heater for annealing trapped charge in a semiconductor device A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heatin... | 06/20/2006 |
| 7045439 | Methods of forming semiconductor constructions The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A se... | 05/16/2006 |
| 7018913 | Method for implanting atomic species through an uneven surface of a semiconductor layer A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes impla... | 03/28/2006 |
| 7015117 | Methods of processing of gallium nitride A method for improving thermal dissipation in large gallium nitride light emitting diodes includes replacing sapphire with a better thermal conductor resulting in more efficient removal of thermal energy. A method for achieving a reliable and strong temporary bond b... | 03/21/2006 |
| 7008860 | Substrate manufacturing method This invention provides a method of manufacturing a substrate having a thin buried insulating film. An insulating layer (12) is formed on a single-crystal Si substrate (11). Ions are implanted into the substrate (11) through the insulating layer... | 03/07/2006 |
| 6964914 | Method of manufacturing a free-standing substrate made of monocrystalline semi-conductor material A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined b... | 11/15/2005 |
| 6936482 | Method of fabricating substrates and substrates obtained by this method Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous ... | 08/30/2005 |
| 6924215 | Method of monitoring high tilt angle of medium current implant A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to t... | 08/02/2005 |
