Class 438/499 - Doping of semiconductor

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process wherein a semiconductive region of the substrate
No. of patents: 31
Last issue date: 02/16/2010

Number	Title	Issue Date
7662705	Partial implantation method for semiconductor manufacturing Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a ...	02/16/2010
7494903	Doped nanoparticle semiconductor charge transport layer A method is disclosed for making a doped semiconductor transport layer for use in an electronic device comprising: growing in-situ doped semiconductor nanoparticles in a colloidal solution; depositing the in-situ doped semiconductor nanoparticles on a surface; and a...	02/24/2009
7459381	Integrated circuits and interconnect structure for integrated circuits A method for reducing parasitic resistance in an integrated circuit, comprises connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively; connecting third and fourth terminals of a second transistor to said...	12/02/2008
7375011	Ex-situ doped semiconductor transport layer A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticl...	05/20/2008
7368317	Method of producing an N-type diamond with high electrical conductivity The invention relates to a method of producing an n-type diamond. The inventive method comprises an n-doping stage during which a donor species is vacuum diffused in a diamond that was initially doped with an acceptor, in order to form donor groups containing the do...	05/06/2008
7352047	Systems and methods for integration of heterogeneous circuit devices A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heteroge...	04/01/2008
7341930	Systems and methods for integration of heterogeneous circuit devices A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heteroge...	03/11/2008
7161198	Semiconductor integrated circuit device having MOS transistor An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a par...	01/09/2007
7052980	Transistor manufacturing method, electrooptical apparatus and electronic apparatus A method for manufacturing a transistor, includes the steps of preparing a substrate, preparing a liquid material containing a silane compound, the silane compound forming a high order silane when photopolymerized, coating the liquid material on the substrate so as ...	05/30/2006
6982212	Method of manufacturing a semiconductor device In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crysta...	01/03/2006
6855991	Semiconductor device having a doped lattice matching layer and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over t...	02/15/2005
6737339	Semiconductor device having a doped lattice matching layer and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over t...	05/18/2004
6686281	Method for fabricating a semiconductor device and a substrate processing apparatus A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3	02/03/2004
6544868	Method of manufacturing light emitting diode with low-receptivity p-type impurity layers formed by microwave treatment The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on ...	04/08/2003
6395653	Semiconductor wafer with crystal lattice defects, and process for producing this wafer A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an un...	05/28/2002
6268271	Method for forming buried layer inside a semiconductor device A method for forming a plurality of buried layers inside a semiconductor device is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Then, the first type p+ -type ions are implanted into the sem...	07/31/2001
6258701	Process for forming insulating structures for integrated circuits A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and ...	07/10/2001
5312764	Method of doping a semiconductor substrate A method of decoupling a step for modulating a defect density from a step for modulating a junction depth. A semiconductor substrate (30) having a portion doped with a dopant (34) is heated to a pre-oxidation anneal temperature in a pre-oxidation anneal s...	05/17/1994
5156982	Pattern shift measuring method A method capable of measuring pattern shift of a semiconductor wafer in a short period of time with utmost ease and in an inexpensive manner is disclosed, wherein a main scale pattern and a vernier scale pattern are formed in parallel spaced confrontation...	10/20/1992
5137838	Method of fabricating P-buried layers for PNP devices A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along wi...	08/11/1992
5010034	CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and N...	04/23/1991
4784964	EPI defect reduction using rapid thermal annealing Formation of defects in epi-layers above buried layers, particularly above arsenic buried layers, is substantially reduced by providing a brief high temperature Rapid Thermal Annealing (RTA) step after buried layer implantation, annealing-activation, and ...	11/15/1988
4381956	Self-aligned buried channel fabrication process A technique is described for the preparation of buried channels of arbitrary conductivity type in a semiconductor device or integrated circuit containing oxide moats in an epitaxial surface layer. By following a specific sequence of process steps, two mas...	05/03/1983
4247862	Ionization resistant MOS structure A structure and method for preventing minority carriers caused by an alpha particle, or the like, from drifting into storage regions and causing a false data bit. In a high density MOS circuit, a single alpha particle including one originating within the ...	01/27/1981
4171995	Epitaxial deposition process for producing an electrostatic induction type thyristor A process of manufacturing a static induction thyristor comprising providing a semiconductor substrate of the first conductivity type which defines a first semiconductor layer and forming a second semiconductor layer thereon of a second conductivity type....	10/23/1979
4155779	Control techniques for annealing semiconductors Polycrystalline and amorphous semiconductors can be annealed using a laser or electron beam to restore or obtain crystal order by epitaxial regrowth on a crystal substrate. When the annealing occurs by liquid phase epitaxy, the presence and lifetime of a ...	05/22/1979
4128440	Liquid phase epitaxial method of covering buried regions for devices Buried regions of predetermined conductivity in silicon semiconductor devices are formed with substantially no out diffusion from the substrate and buried region, and with substantially no lateral autodoping, by diffusing the region into a monocrystalline...	12/05/1978
4082571	Process for suppressing parasitic components utilizing ion implantation prior to epitaxial deposition A process for suppressing parasitic components, in particular parasitic diodes and transistors, in integrated circuits which have, in particular, inversely operated transistors, in which a semiconductor substrate of the first conductivity type as introduc...	04/04/1978
3976512	Method for reducing the defect density of an integrated circuit utilizing ion implantation The buried layer of an integrated circuit is produced by use of a grated mask. The growth of silicon dioxide in the exposed areas of the grate forms a stepped surface. Thereafter ion implantation in these areas and then merging the implanted regions forms...	08/24/1976
3945856	Method of ion implantation through an electrically insulative material A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energ...	03/23/1976
3945030	Semiconductor structure having contact openings with sloped side walls Semiconductor structure having a semiconductor body with a planar surface. At least one region having an impurity therein is formed in the body and extends to the surface. A layer of insulating material is provided on the surface. Openings are formed in t...	03/16/1976

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Class 438/499 - Doping of semiconductor