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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7595260 | Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices A bulk-doped semiconductor may be at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk... | 09/29/2009 |
| 7344909 | Method for producing semi-conducting devices and devices obtained with this method A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of... | 03/18/2008 |
| 7341787 | Process for producing highly doped semiconductor wafers, and dislocation-free highly doped semiconductor wafers The invention relates to a process for producing highly doped semiconductor wafers, in which at least two dopants which are electrically active and belong to the same group of the periodic system of the elements are used for the doping. The invention also relates to... | 03/11/2008 |
| 7268079 | Method for fabricating a semiconductor having a field zone A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in... | 09/11/2007 |
| 7160748 | Method for fabricating nitride semiconductor, method for fabricating nitride semiconductor device, and nitride semiconductor device The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrog... | 01/09/2007 |
| 7135387 | Method of manufacturing semiconductor element A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively com... | 11/14/2006 |
| 7098521 | Reduced guard ring in schottky barrier diode structure Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integr... | 08/29/2006 |
| 7094670 | Plasma immersion ion implantation process A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersi... | 08/22/2006 |
| 7064399 | Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran... | 06/20/2006 |
| 7026642 | Vertical tunneling transistor The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may ... | 04/11/2006 |
| 6982212 | Method of manufacturing a semiconductor device In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crysta... | 01/03/2006 |
| 6921678 | Method for fabricating nitride semiconductor, method for fabricating nitride semiconductor device, and nitride semiconductor device The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrog... | 07/26/2005 |
| 6916698 | High performance CMOS device structure with mid-gap metal gate High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices... | 07/12/2005 |
| 6911367 | Methods of forming semiconductive materials having flattened surfaces; methods of forming isolation regions; and methods of forming elevated source/drain regions The invention includes methods of forming epitaxially-grown semiconductive material having a flattened surface, and methods of incorporating such material into trenched regions and elevated/source drain regions. A method of forming epitaxially-grown semiconductive m... | 06/28/2005 |
| 6890816 | Compound semiconductor structure including an epitaxial perovskite layer and method for fabricating semiconductor structures and devices High quality epitaxial layers of monocrystalline perovskite materials (18) can be grown overlying monocrystalline substrates (12) such as gallium arsenide wafers by forming a metal template layer (16) on the monocrystalline substrate. The struct... | 05/10/2005 |
| 6855991 | Semiconductor device having a doped lattice matching layer and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over t... | 02/15/2005 |
| 6776842 | Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including... | 08/17/2004 |
| 6740547 | Method for fabricating thin-film transistor A process for fabricating thin film transistors is disclosed, which comprises a two-step laser annealing process as follows: crystallizing the channel portion by irradiating the channel portion with an irradiation beam; and modifying the electric prope... | 05/25/2004 |
| 6737339 | Semiconductor device having a doped lattice matching layer and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over t... | 05/18/2004 |
| 6716690 | Uniformly doped source/drain junction in a double-gate MOSFET Multiple dopant implantations are performed on a FinFET device to thereby distribute the dopant in a substantially uniform manner along a vertical depth of the FinFET in the source/drain junction. Each of the multiple implantations may be performed at different tilt... | 04/06/2004 |
| 6686281 | Method for fabricating a semiconductor device and a substrate processing apparatus A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3 | 02/03/2004 |
| 6635956 | Semiconductor device, semiconductor module and hard disk A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting memb... | 10/21/2003 |
| 6593217 | Method of manufacturing semiconductor device A semiconductor device with low contact resistance which can cope with the miniaturization of semiconductor devices as well as a manufacturing method thereof which is easy and inexpensive can be obtained. Impurity regions on an Si substrate, an interlayer... | 07/15/2003 |
| 6465333 | Method of manufacturing a circuit When the temperature of a silicon substrate is increased, a first annealing gas which is mainly composed of argon or the like that does not react with said silicon substrate with a trace of oxygen added thereto, is supplied to the position of the silicon ... | 10/15/2002 |
| 6387779 | Method of crystallizing a silicon film and thin film transistor and fabricating method thereof using the same The present invention relates to a method of crystallizing a silicon film, a thin film transistor, and a fabricating method thereof using the same. More particularly, the present invention relates forming a crystalline silicon film by crystallizing a sili... | 05/14/2002 |
| 6379990 | Method of fabricating a micromechanical semiconductor configuration A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrat... | 04/30/2002 |
| 6228181 | Making epitaxial semiconductor device An epitaxial semiconductor wafer characterized by making the P-N junction face which having either flat or uneven face in a manner of uniformed thickness from the top surface, due to making a P or N type first layer by the Chemical Vapor Deposition on the... | 05/08/2001 |
| 6162706 | Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic... | 12/19/2000 |
| 6043139 | Process for controlling dopant diffusion in a semiconductor layer Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.... | 03/28/2000 |
| 6010937 | Reduction of dislocations in a heteroepitaxial semiconductor structure A heteroepitaxial semiconductor device having reduced density of threading dislocations and a process for forming such a device. According to one embodiment, the device includes a substrate which is heat treated to a temperature in excess of 1000° C., a ... | 01/04/2000 |
| 6008110 | Semiconductor substrate and method of manufacturing same A semiconductor substrate has a support substrate formed of monocrystal silicon, an oxide film formed on the support substrate and a thin film of monocrystal silicon formed on the oxide film. The support substrate is a high-concentration P-type substrate ... | 12/28/1999 |
| 5967795 | SiC semiconductor device comprising a pn junction with a voltage absorbing edge A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise o... | 10/19/1999 |
| 5913107 | Photosemiconductor device and method of fabricating the same A pair of SiO2 stripe masks are formed on a p-InP substrate (31) with a separation of 1.5 μm in 011! direction and an optical waveguide including a p-InP clad layer (32), an active layer (33) and an n-InP clad layer (34) is formed on the p-I... | 06/15/1999 |
| 5756375 | Semiconductor growth method with thickness control Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, a... | 05/26/1998 |
| 5733815 | Process for fabricating intrinsic layer and applications A method of simultaneously forming a gallium arsenide p-i-n structure having p, i, and n regions, which includes heating to dissolve gallium arsenide in a solvent such as bismuth or gallium to form a saturated solution of gallium arsenide in the solvent, ... | 03/31/1998 |
| 5710058 | Method of making multi-terminal resonant tunneling transistor A transistor according to the invention for simultaneously providing at least two current-voltage characteristics includes a base, a collector, and an emitter. At least one of the base, collector, and emitter includes a first layer grown using molecular b... | 01/20/1998 |
| 5705406 | Method for producing a semiconductor device having semiconductor layers of SiC by the use of an ion-implantation technique A method for producing a semiconductor device having semiconductor layers of SiC with at least three doped layers on top of each other, comprises the steps of growing a first semiconductor layer of SiC; implanting an impurity dopant into the first layer t... | 01/06/1998 |
| 5633180 | Method of forming P-type islands over P-type buried layer A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transi... | 05/27/1997 |
| 5330922 | Semiconductor process for manufacturing semiconductor devices with increased operating voltages A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substanti... | 07/19/1994 |
| 5298441 | Method of making high transconductance heterostructure field effect transistor A high transconductance HFET (21) utilizes nonalloy semiconductor materials (26) to form a strained channel layer (26) that has a deep quantum well (38). The materials utilized for layers adjacent to the channel layer (26) apply strain to the channel laye... | 03/29/1994 |
