Class 438/494 - Differential etching

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process where the differential etching of the substrate
No. of patents: 129
Last issue date: 06/07/2011

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Number	Title	Issue Date
7955959	Method for manufacturing GaN-based film LED A method for manufacturing GaN-based film LED based on masklessly transferring photonic crystal structure is disclosed. Two dimensional photonic crystals are formed on a sapphire substrate. Lattice quality of GaN-based epitaxy on the sapphire substrate is improved, ...	06/07/2011
7902053	Method of processing semiconductor wafer Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity co...	03/08/2011
7767560	Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first ...	08/03/2010
7439142	Methods to fabricate MOSFET devices using a selective deposition process In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsi...	10/21/2008
7372087	Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration o...	05/13/2008
7371627	Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar ext...	05/13/2008
7344997	Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and f...	03/18/2008
7268079	Method for fabricating a semiconductor having a field zone A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in...	09/11/2007
7250359	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer....	07/31/2007
7241647	Graded semiconductor layer A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion an...	07/10/2007
7202139	MOSFET device with a strained channel An ultra thin MOSFET device structure located on an insulator layer, and a method of forming the ultra thin MOSFET device structure featuring a strained silicon channel located on the underlying insulator layer, has been developed. After epitaxial growth of a semico...	04/10/2007
7189592	Manufacturable single-chip hydrogen sensor A robust single-chip hydrogen sensor and a method for fabricating such a sensor. By utilizing an interconnect metallization material that is the same or similar to the material used to sense hydrogen, or that is capable of withstanding an etchant used to pattern a h...	03/13/2007
7147709	Non-contact etch annealing of strained layers The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice con...	12/12/2006
7084041	Bipolar device and method of manufacturing the same including pre-treatment using germane gas A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon laye...	08/01/2006
7071087	Technique to grow high quality ZnSe epitaxy layer on Si substrate A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1−x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe ...	07/04/2006
7060516	Method for integrating optical devices in a single epitaxial growth step A method for integrating optical devices in a single growth step by utilizing a combination of Selective Area Growth and Etch (SAGE) is provided. An first device is formed between a set of oxide-masked regions, whilst a second device is formed in an adjacent planar ...	06/13/2006
7060632	Methods for fabricating strained layers on semiconductor substrates Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that ca...	06/13/2006
7056789	Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, pr...	06/06/2006
7022592	Ammonia-treated polysilicon semiconductor device Semiconductor devices, and methods of fabricating, having ammonia-treated polysilicon devices are provided. A substrate is provided upon which a polysilicon layer is formed. The polysilicon layer is treated with ammonia. Thereafter, portions of the polysilicon layer...	04/04/2006
7022593	SiGe rectification process A method for forming strain-relaxed SiGe films comprises depositing a graded strained SiGe layer on a substrate in which the concentration of Ge is greater at the interface with the substrate than at the top of the layer. The strained SiGe film is subsequently oxidi...	04/04/2006
7012011	Wafer-level diamond spreader An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization i...	03/14/2006
6967112	Three-dimensional quantum dot structure for infrared photodetection A 3D quantum dot optical path structure is provided, along with a method for selectively forming a 3D quantum dot optical path. The method comprises: forming a single crystal Si substrate with a surface; forming a Si feature in the substrate, such as a via, trench, ...	11/22/2005
6955952	Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain w...	10/18/2005
6946371	Methods of fabricating semiconductor structures having epitaxially grown source and drain elements Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on...	09/20/2005
6942731	Method for improving the efficiency of epitaxially produced quantum dot semiconductor components The invention relates to a method for improving the efficiency of epitaxially grown quantum dot semiconductor components having at least one quantum dot layer. The efficiency of semiconductor components containing an active medium consisting of quantum dots is often...	09/13/2005
6927103	Method and apparatus of terminating a high voltage solid state device Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between differ...	08/09/2005
6858907	Method of fabricating semiconductor device having notched gate A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region;...	02/22/2005
6740583	Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are pro...	05/25/2004
6699795	Gate etch process A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a s...	03/02/2004
6555482	Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of ...	04/29/2003
6388253	Integrated critical dimension control for semiconductor device manufacturing A method and apparatus for reducing lot to lot CD variation in semiconductor wafer processing feeds back information gathered during inspection of a wafer, such as after photoresist application, exposure and development, to upcoming lots that will be goin...	05/14/2002
6369396	Calibration target for electron beams A scattering target for use in a particle beam system is formed from a grid of gold on a substrate of carbon, with an intermediate smoothing layer (e.g. copper) on the carbon to provide a surface sufficiently smooth to provide an adequate target. An optio...	04/09/2002
6362474	Semiconductor sample for transmission electron microscope and method of manufacturing the same Described here is a method of forming a thin-film portion for allowing electrons produced from a transmission electron microscope to pass therethrough at a portion to be observed of a semiconductor and effecting a predetermined etching process on the thin...	03/26/2002
6291321	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one f...	09/18/2001
6171935	Process for producing an epitaxial layer with laterally varying doping A process for producing an epitaxial layer with laterally varying doping includes the following steps: (a) applying a patterned insulator layer to a semiconductor body; (b) growing a first epitaxial layer on the semiconductor body and the patterned insula...	01/09/2001
6100172	Method for forming a horizontal surface spacer and devices formed thereby The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an impl...	08/08/2000
6033995	Inverted layer epitaxial liftoff process The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) ...	03/07/2000
5967795	SiC semiconductor device comprising a pn junction with a voltage absorbing edge A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise o...	10/19/1999
5918128	Reduced channel length for a high performance CMOS transistor An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the gate conductor using a photolithographic process, the lateral...	06/29/1999
5880012	Method for making semiconductor nanometer-scale wire using an atomic force microscope The present invention provides a method for making semiconductor nanometer-scale wire. The method comprises the steps of: forming a nitride film on a semiconductor substrate by implanting a nitrogen ions at a high temperature; forming a nitride film patte...	03/09/1999

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Class 438/494 - Differential etching