Bizarre Patents
An aircraft having vertical takeoff and landing capability provided with at least first and second laterally extending paddle wheels rotatable on a central axis perpendicular to the longitudinal axis of the aircraft fuselage and between its nose and tail.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7879686 | Semiconductor device and method for manufacturing A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the firs... | 02/01/2011 |
| 7662698 | Transistor having field plate A method for forming a transistor device having a field plate. The method includes forming a structure having a source, a drain, and a Tee gate. A photo-resist layer is formed on the structure with an opening therein only the one of two distal ends of the Tee gate. ... | 02/16/2010 |
| 7368380 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is disclosed in which a metallic deposit is stably formed on the anode side with small variation in film thickness, and plating is prevented on the cathode side without carrying out any additional processing on the ca... | 05/06/2008 |
| 7352548 | Composite integrated semiconductor device A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit ... | 04/01/2008 |
| 7351661 | Semiconductor device having trench isolation layer and a method of forming the same A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer fo... | 04/01/2008 |
| 7335565 | Metal-oxide-semiconductor device having improved performance and reliability A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and... | 02/26/2008 |
| 7287326 | Methods of forming a contact pin assembly A compliant contact pin assembly method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The... | 10/30/2007 |
| 7282906 | Electronic circuit protection device A device for protecting an electronic circuit comprising a support to which are attached at least two circuit portions, each comprising at least one integrated circuit chip. The device comprises a wafer of a semiconductor material covered with a conductive layer arr... | 10/16/2007 |
| 7253486 | Field plate transistor with reduced field plate resistance In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The f... | 08/07/2007 |
| 7190052 | Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor material A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures are exposed. The semiconductor device structure is formed by selectively forming the passivation layer on an exposed silicon-comprising surface by expo... | 03/13/2007 |
| 7179712 | Multibit ROM cell and method therefor To increase the density of memory cells, a multibit memory cell (10, 50, 80, 110) can be manufactured by preventing the formation of at least one of the extension regions usually formed for the source or drain region. In one embodiment, a single mask (24 | 02/20/2007 |
| 7101770 | Capacitive techniques to reduce noise in high speed interconnections Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabr... | 09/05/2006 |
| 7071515 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the t... | 07/04/2006 |
| 7061059 | Semiconductor device The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for e... | 06/13/2006 |
| 7049669 | LDMOS transistor A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first conductivity type extending from a surface of the active region into the active region and substantially surroundin... | 05/23/2006 |
| 7005703 | Metal-oxide-semiconductor device having improved performance and reliability An MOS device includes a semiconductor layer comprising a substrate of a first conductivity type and a second layer of a second conductivity type formed on at least a portion of the substrate. First and second source/drain regions of the second conductivity type are... | 02/28/2006 |
| 6979644 | Method of manufacturing electronic circuit component A method of manufacturing an electronic circuit component, including the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at le... | 12/27/2005 |
| 6965166 | Semiconductor device of chip-on-chip structure A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to... | 11/15/2005 |
| 6955970 | Process for manufacturing a low voltage MOSFET power device having a minimum figure of merit A power MOSFET die with a minimized figure of merit has of a planar stripe MOSFET geometry in which parallel diffused bases (or channels) are formed by implantation and diffusion of impurities through parallel elongated and spaced polysilicon stripes wherein the pol... | 10/18/2005 |
| 6951806 | Metal region for reduction of capacitive coupling between signal lines A structure includes a substrate, first and second signal lines above the substrate, where unused substrate surface area exists between the first and second signal lines, and a first shield line in the unused substrate surface area. To define the first shield line, ... | 10/04/2005 |
| 6939781 | Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (42... | 09/06/2005 |
| 6927103 | Method and apparatus of terminating a high voltage solid state device Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between differ... | 08/09/2005 |
| 6927141 | Process for forming fast recovery diode with a single large area P/N junction A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periph... | 08/09/2005 |
| 6916699 | Device and method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 07/12/2005 |
| 6906381 | Lateral semiconductor device with low on-resistance and method of making the same A lateral semiconductor device (20) such as LDMOS, a LIGBT, a lateral diode, a lateral GTO, a lateral JFET or a lateral BJT, comprising a drift region (12) having a first surface (22) and a first conductivity type, first and second conductive ( | 06/14/2005 |
| 6878578 | Method for forming a high quality chemical oxide on a freshly cleaned silicon surface as a native oxide replacement A continuous and integrated cleaning/preparation process is described to condition a silicon surface for the formation of a high quality ultra thin gate oxide described. The process is conducted with the wafer surface immersed in an aqueous solution the composition ... | 04/12/2005 |
| 6849908 | Semiconductor device and method of manufacturing the same A good interface characteristic can be maintained, and a leakage current of a dielectric film can be decreased. A semiconductor device according to one aspect of the present invention includes: a semiconductor substrate; a gate dielectric film containing at least ni... | 02/01/2005 |
| 6844236 | Method and structure for DC and RF shielding of integrated circuits A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a gro... | 01/18/2005 |
| 6844241 | Fabrication of semiconductor structures having multiple conductive layers in an opening In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments,... | 01/18/2005 |
| 6806123 | Methods of forming isolation regions associated with semiconductor constructions The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-t... | 10/19/2004 |
| 6756619 | Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 06/29/2004 |
| 6734496 | Semiconductor device A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurali... | 05/11/2004 |
| 6713846 | Multilayer high κ dielectric films A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal oxide material having a high dielectric constant, and a second layer fo... | 03/30/2004 |
| 6709900 | Method of fabricating integrated system on a chip protection circuit A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control c... | 03/23/2004 |
| 6682962 | GaAs MOSFET having low capacitance and on-resistance and method of manufacturing the same A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a ga... | 01/27/2004 |
| 6682989 | Plating a conductive material on a dielectric material A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions... | 01/27/2004 |
| 6656781 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, HAVING FIRST AND SECOND SEMICONDUCTOR REGIONS WITH FIELD SHIELD ISOLATION STRUCTURES AND A FIELD OXIDE FILM COVERING A JUNCTION BETWEEN SEMICONDUCTOR REGIONS A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover th... | 12/02/2003 |
| 6638833 | Process for the fabrication of integrated devices with reduction of damage from plasma The process for the fabrication of an electronic device has the steps of forming a layer to be etched on top of a substrate in a wafer of semiconductor material; depositing a masking layer; and carrying out a plasma etch to define the geometry of the laye... | 10/28/2003 |
| 6597044 | Semiconductor device having a charge removal facility for minority carriers The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the... | 07/22/2003 |
| 6586283 | Apparatus and method for protecting integrated circuit charge storage elements from photo-induced currents An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, a... | 07/01/2003 |
