Quotables
"The wireless music box has no imaginable commercial value. Who would pay for a message sent to nobody in particular?"
David Sarnoff, American radio pioneer ; 1921
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8187952 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so tha... | 05/29/2012 |
| 7655536 | Methods of forming flash devices with shared word lines Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that periphe... | 02/02/2010 |
| 7582539 | Methods of cleaning a semiconductor device and methods of manufacturing a semiconductor device using the same The present invention provides methods of cleaning a semiconductor device by removing contaminants, such as particles and/or etching by-products, from a structure of a semiconductor device using a first cleaning solution including a mixture of ammonium hydroxide (NH... | 09/01/2009 |
| 7425489 | Self-aligned shallow trench isolation A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer... | 09/16/2008 |
| 7382363 | Microencapsulated electrophoretic display with integrated driver A mounted display assembly comprises a flexible substrate that supports both display elements and control circuits. The display assembly generally comprises: an electrical connection formed on the flexible substrate, the electrical connection having first and second... | 06/03/2008 |
| 7358151 | Microelectromechanical system microphone fabrication including signal processing circuitry on common substrate A MEMS microphone is formed on a single substrate that also includes microelectronic circuitry. High-temperature tolerance metals are used to form contacts in a metallization step before performing deep reactive ion etching and back patterning steps to form a MEMS m... | 04/15/2008 |
| 7358184 | Method of forming a conductive via plug A method of forming a conductive via plug is disclosed. The conductive via plug is formed by printing a solution comprising a solvent with insulating material dissolve capability and a conductive material by an inkjet method. The formed conductive via plug has a low... | 04/15/2008 |
| 7300835 | Manufacturing method of semiconductor device A method of manufacturing a semiconductor device including forming a gate oxide layer, a first conductive layer, a capacitor dielectric layer, and a second conductive layer on a semiconductor substrate. The method also includes patterning the first and second conduc... | 11/27/2007 |
| 7279396 | Methods of forming trench isolation regions with nitride liner The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is form... | 10/09/2007 |
| 7241705 | Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field eff... | 07/10/2007 |
| 7214594 | Method of making semiconductor device using a novel interconnect cladding layer A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive in... | 05/08/2007 |
| 7164204 | Integrated circuit devices with an auxiliary pad for contact hole alignment An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and... | 01/16/2007 |
| 7160406 | Ceramic substrate and method for the production thereof A process for producing a ceramic substrate includes preparing a base body using a stack of layers that contain an unsintered ceramic material and a sintering agent, and sintering the stack of layers. At least one of the layers contains an increased proportion of si... | 01/09/2007 |
| 7153722 | Method and apparatus for manufacturing photovoltaic device A method of manufacturing a photovoltaic device includes: a step of fixing thin metal wires which are coated with electroconductive resin, to a principal surface of a photovoltaic member; a step of heating the photovoltaic member to which the thin metal wires are fi... | 12/26/2006 |
| 7151041 | Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor subs... | 12/19/2006 |
| 7115464 | Semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be form... | 10/03/2006 |
| 7105389 | Method of manufacturing semiconductor device having impurity region under isolation region In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film | 09/12/2006 |
| 7087983 | Manufacturing methods of semiconductor devices and a solid state image pickup device A manufacturing method of manufacturing a semiconductor device having a plurality of wiring layers. The method includes the steps of forming a wiring by a first wiring layer as a pattern by dividing a desired pattern into a plurality of patterns, connecting the divi... | 08/08/2006 |
| 7084058 | Method of forming low-loss coplanar waveguides Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over a silicon substrate and a photoresist is applied and patterned to define areas where the signal line and... | 08/01/2006 |
| 7078313 | Method for fabricating an integrated semiconductor circuit to prevent formation of voids Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can... | 07/18/2006 |
| 7067414 | Low k interlevel dielectric layer fabrication methods A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3... | 06/27/2006 |
| 7067850 | Stacked switchable element and diode combination A device (10) comprises a semiconductor diode (12) and a switchable element (14) positioned in stacked adjacent relationship so that the semiconductor diode (12) and the switchable element (14) are electrically connected in series ... | 06/27/2006 |
| 7067368 | Method for forming self-aligned dual salicide in CMOS technologies A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semicon... | 06/27/2006 |
| 7041586 | Semiconductor device having a multilayer interconnection structure A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-gl... | 05/09/2006 |
| 7030014 | Semiconductor constructions and electronic systems comprising metal silicide The invention includes methods of forming metal silicide having bulk resistance of less than 30 micro-ohms-centimeter. The metal of the metal silicide can be selected from Groups 3, 4, 8, 9 and 10 of the periodic table, with an exemplary metal being titanium. An exe... | 04/18/2006 |
| 7023501 | Liquid crystal display device having particular connections among drain and pixel electrodes and contact hole A liquid crystal display device and a method of fabricating the same are disclosed. The device, as disclosed, reduces the number of masks required to fabricate. Thus, cost is reduced and yield is increased. The device includes a plurality of gate lines, a plurality ... | 04/04/2006 |
| 7022565 | Method of fabricating a trench capacitor of a mixed mode integrated circuit A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric laye... | 04/04/2006 |
| 6967151 | Method of manufacturing a semiconductor device Provided is a method of manufacturing a semiconductor device. In the method, an insulation spacer is formed thicker than a target thickness on sidewalls of a gate line formed on a semiconductor substrate. The thickness of the insulation spacer is adjusted by means o... | 11/22/2005 |
| 6953749 | Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restric... | 10/11/2005 |
| 6951791 | Global column select structure for accessing a memory An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer i... | 10/04/2005 |
| 6930901 | Method of selectively forming local interconnects using design rules The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon... | 08/16/2005 |
| 6919619 | Actively-shielded signal wires A system and method is provided that improves the propagation characteristics of an electrical conducting signal wire on an integrated circuit. The system includes a pair of parallel shielding wires positioned on opposite longitudinal sides of the signal wire. A shi... | 07/19/2005 |
| 6905923 | Offset spacer process for forming N-type transistors A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with ... | 06/14/2005 |
| 6869856 | Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually a... | 03/22/2005 |
| 6869867 | SEMICONDUCTOR DEVICE COMPRISING METAL SILICIDE FILMS FORMED TO COVER GATE ELECTRODE AND SOURCE-DRAIN DIFFUSION LAYERS AND METHOD OF MANUFACTURING THE SAME WHEREIN THE SILICIDE ON GATE IS THICKER THAN ON SOURCE-DRAIN The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semicon... | 03/22/2005 |
| 6777290 | Global column select structure for accessing a memory An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer i... | 08/17/2004 |
| 6770541 | Method for hard mask removal for deep trench isolation and related structure According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench ha... | 08/03/2004 |
| 6750107 | Method and apparatus for isolating a SRAM cell A static random access memory cell comprising a first inverter including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second inverter including a second p-channel pullup transi... | 06/15/2004 |
| 6709926 | High performance logic and high density embedded dram with borderless contact and antispacer An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without c... | 03/23/2004 |
| 6706617 | Method for forming isolation pattern in semiconductor device A method enables a hole-type LPC mask to be employed instead of the conventional T-type LPC mask, thereby reducing time and manpower for the manufacture of the mask. The method comprises the steps of: arranging a plurality of bit lines at regular intervals in a long... | 03/16/2004 |
