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| Number | Title | Issue Date |
| 7972934 | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main sur... | 07/05/2011 |
| 7541260 | Trench diffusion isolation in semiconductor devices A semiconductor structure is formed comprising a plurality of columns doped with alternating dopants. The columns are separated by trenches, and the dopant is diffused in the doped columns. The trenches are filled with semiconductor material. Other embodiments may b... | 06/02/2009 |
| 7422924 | Image device and photodiode structure The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation re... | 09/09/2008 |
| 7361540 | Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone... | 04/22/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7262111 | Method for providing a deep connection to a substrate or buried layer in a semiconductor device A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created ... | 08/28/2007 |
| 7235460 | Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t... | 06/26/2007 |
| 7211863 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 05/01/2007 |
| 7202536 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 04/10/2007 |
| 7170126 | Structure of vertical strained silicon devices A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces res... | 01/30/2007 |
| 7135738 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 11/14/2006 |
| 7056816 | Method for manufacturing semiconductor device A mask layer having an opening is formed on a semiconductor substrate. Next, oxygen ions and a first impurity are implanted into the semiconductor substrate using the mask layer as a mask. Then, the mask layer is removed. Next, the oxygen ions are heat treated to re... | 06/06/2006 |
| 7015527 | Metal oxynitride capacitor barrier layer Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures ... | 03/21/2006 |
| 7005340 | Method for manufacturing semiconductor device A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps. The method comprises the steps of: (a) forming a first mask layer... | 02/28/2006 |
| 7002202 | Metal oxynitride capacitor barrier layer Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures ... | 02/21/2006 |
| 6979587 | Image sensor and method for fabricating the same The present invention provides an image sensor capable of suppressing the dark current due to crystalline defects occurring at an edge of a field oxide layer and a method for fabricating the same. The present invention provides an image sensor including: a semicondu... | 12/27/2005 |
| 6979616 | Method for fabricating semiconductor device with dual gate dielectric structure Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for th... | 12/27/2005 |
| 6977204 | Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do... | 12/20/2005 |
| 6958521 | Shallow trench isolation structure Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A secon... | 10/25/2005 |
| 6946338 | Method for manufacturing semiconductor device The present invention discloses a method for manufacturing semiconductor device wherein a channel implant process of a transistor in a DRAM is performed in a self-aligned manner without using any mask. In accordance with the method, a device isolation film defining ... | 09/20/2005 |
| 6936897 | Intermediate structure having a silicon barrier layer encapsulating a semiconductor substrate A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of a substrate. A pad oxide film is grown on the first surface of the substrate covering the p-wells and/or n-wells. A di... | 08/30/2005 |
| 6908810 | Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region... | 06/21/2005 |
| 6900091 | Isolated complementary MOS devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 05/31/2005 |
| 6846722 | Method for isolating a hybrid device in an image sensor The present disclosure relates to a method for fabricating an image sensor capable of improving dark current characteristics. The method includes: forming sequentially a pad oxide layer and a pad nitride layer on a substrate and selectively removing a portion of the... | 01/25/2005 |
| 6844226 | System and method to reduce noise in a substrate Aspects of the method for reducing noise in the substrate may comprise doping a substrate with a first dopant and doping a first well disposed on the substrate with a second dopant. The first well may be a deep well. A second well disposed within the first well may ... | 01/18/2005 |
| 6815287 | Localized array threshold voltage implant to enhance charge storage within DRAM memory cells A DRAM device having improved charge storage capabilities and methods for providing the same. The device includes an array portion having a plurality of memory cells extending from a semiconductor substrate. Each cell includes a storage element for storing a quantit... | 11/09/2004 |
| 6790700 | Image sensor and method for fabricating the same The present invention provides an image sensor capable of suppressing the dark current due to crystalline defects occurring at an edge of a field oxide layer and a method for fabricating the same. The present invention provides an image sensor including: a semicondu... | 09/14/2004 |
| 6730569 | Field effect transistor with improved isolation structures An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from th... | 05/04/2004 |
| 6703187 | Method of forming a self-aligned twin well structure with a single mask An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process su... | 03/09/2004 |
| 6696351 | Semiconductor device having a selectively deposited conductive layer A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circu... | 02/24/2004 |
| 6677223 | Transistor with highly uniform threshold voltage Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentrati... | 01/13/2004 |
| 6660595 | Implantation method for simultaneously implanting in one region and blocking the implant in another region A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is sub... | 12/09/2003 |
| 6472279 | Method of manufacturing a channel stop implant in a semiconductor device The present invention provides a method of manufacturing a semiconductor device, and a related method manufacturing an integrated circuit. In one embodiment, the method of manufacturing a semiconductor device includes creating a source/drain region betwee... | 10/29/2002 |
| 6362035 | Channel stop ion implantation method for CMOS integrated circuits A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. T... | 03/26/2002 |
| 6346464 | Manufacturing method of semiconductor device A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectiv... | 02/12/2002 |
| 6309921 | Semiconductor device and method for fabricating semiconductor device The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a s... | 10/30/2001 |
