Celebrity Inventors
Walt Disney was no Mickey Mouse inventor. He devised a serious animation camera which he patented. With the device, his company created "Snow White".
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7989311 | Strained semiconductor by full wafer bonding One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonde... | 08/02/2011 |
| 7867872 | Method for manufacturing semiconductor device with uniform concentration ion doping in recess gate channel region A semiconductor device is manufactured by defining a groove in a semiconductor substrate, where the groove includes an upper portion and a lower portion, among other steps. A sacrificial layer is then formed to selectively fill the lower portion of the groove. Impur... | 01/11/2011 |
| 7704855 | Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress tra... | 04/27/2010 |
| 7666756 | Methods of fabricating isolation structures in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/23/2010 |
| 7439158 | Strained semiconductor by full wafer bonding One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonde... | 10/21/2008 |
| 7425752 | Semiconductor device channel termination A semiconductor device has a channel termination region for using a trench (30) filled with field oxide (32) and a channel stopper ring (18) which extends from the first major surface (8) through p-well (6) along the outer edge ( | 09/16/2008 |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7309620 | Use of sacrificial layers in the manufacture of high performance systems on tailored substrates The invention relates to methods for preparing a removable system on a mother substrate. The method deposits a high surface to volume sacrificial layer on a mother substrate and stabilizes the sacrificial layer by a) removing volatile chemical species in and on the ... | 12/18/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7271462 | Solid-state image sensing device A solid-state image sensing device that is free of kTC noise, can eliminate black smear and dark current, has a larger numerical aperture, and can eliminate the problem of insufficient area of the light-receiving portion. Photodiode PD is formed as the light-receivi... | 09/18/2007 |
| 7253047 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 08/07/2007 |
| 7214591 | Method of fabricating high-voltage MOS device A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying d... | 05/08/2007 |
| 7183167 | Semiconductor device having a trench isolation and method of fabricating the same The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to h... | 02/27/2007 |
| 7147740 | Method of transferring a laminate and method of manufacturing a semiconductor device An object of the present invention is to provide a method of transferring an object to be peeled onto a transferring member in a short time without imparting damage to the object to be peeled within a laminate. Also, another object of the present invention is to pro... | 12/12/2006 |
| 7122095 | Methods for forming an assembly for transfer of a useful layer Methods for forming an assembly for transfer of a useful layer are described. In an embodiment, the method includes forming a useful layer on a first support having an interface therebetween, and a residual material on a portion of the first support to form the asse... | 10/17/2006 |
| 7067387 | Method of manufacturing dielectric isolated silicon structure A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon substrate and trenches of required dimensions are etched into silicon. Afte... | 06/27/2006 |
| 7064387 | Silicon-on-insulator (SOI) substrate and method for manufacturing the same A silicon-on-insulator (SOI) substrate includes a silicon substrate including an active region defined by a field region that surrounds the active region for device isolation. The field region includes a first oxygen-ion-injected isolation region and a second oxygen... | 06/20/2006 |
| 7061128 | Semiconductor device and manufacturing method of the same A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; a gate electrode formed on the active region with an oxide film interposed therebetween; and a set of impurity regions f... | 06/13/2006 |
| 7060590 | Layer transfer method The invention relates to a method of removing a peripheral zone of adhesive while using a layer of adhesive in the process of assembling and transferring a layer of material from a source substrate to a support substrate. The method is remarkable in that it includes... | 06/13/2006 |
| 7052919 | Recipe cascading in a wafer processing system The invention allows a cluster tool to change from a first recipe to a second recipe, while preserving periodicity and ensuring that there are no delays at critical points. This procedure is referred to as recipe cascading. Cascading involves emptying a first lot of... | 05/30/2006 |
| 7041575 | Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi... | 05/09/2006 |
| 7037814 | Single mask control of doping levels In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the m... | 05/02/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 6991983 | Method of manufacturing high voltage transistor in flash memory device Disclosed is a method of manufacturing a high voltage transistor in a flash memory device. The method can prohibit a punch leakage current of an isolation film while satisfying active characteristics of the high voltage transistor without the need for a mask process... | 01/31/2006 |
| 6965147 | Semiconductor device including transistors formed in semiconductor layer having single-crystal structure isolated from substrate A semiconductor device includes a substrate, a semiconductor layer of a first conductivity type having a single-crystal structure, and a plurality of transistors each including a first gate electrode provided above the semiconductor layer with a first gate insulatio... | 11/15/2005 |
| 6962728 | Method for forming ONO top oxide in NROM structure A method for making a silicon oxide/silicon nitride/silicon oxide structure includes forming a tunnel oxide layer and a silicon nitride layer over a substrate; annealing the silicon nitride layer; forming a silicon oxide layer over the annealed silicon nitride layer... | 11/08/2005 |
| 6952622 | Robot pre-positioning in a wafer processing system A wafer cluster tool is described which operates in a regular, periodic fashion. Embodiments of the invention have a periodicity of one sending period. The invention enables the determination of pick-up times for process chambers in the cluster tool, and embodiments... | 10/04/2005 |
| 6875663 | Semiconductor device having a trench isolation and method of fabricating the same The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to h... | 04/05/2005 |
| 6797587 | Active region corner implantation method for fabricating a semiconductor integrated circuit microelectronic fabrication Within a method for forming an isolation region within a semiconductor substrate, there is, prior to forming the isolation region within an isolation trench formed adjoining an active region of a semiconductor substrate, implanted a dopant into a corner of the activ... | 09/28/2004 |
| 6790752 | Methods of controlling VSS implants on memory devices, and system for performing same The present invention is generally directed to various methods of controlling Vss implants on memory devices, and a system for performing same. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substr... | 09/14/2004 |
| 6713334 | Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS co... | 03/30/2004 |
| 6696351 | Semiconductor device having a selectively deposited conductive layer A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circu... | 02/24/2004 |
| 6660595 | Implantation method for simultaneously implanting in one region and blocking the implant in another region A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is sub... | 12/09/2003 |
| 6613639 | Forming a semiconductor on implanted insulator A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion... | 09/02/2003 |
| 6596609 | Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer A method of fabricating a feature on a substrate is disclosed. In a described embodiment the feature is the gate electrode of an MOS transistor. In this embodiment a polysilicon layer is formed on the substrate. Next, an edge definition layer of silicon n... | 07/22/2003 |
| 6583018 | Method of ion implantation An ion implantation method which can accurately control the effective dose amount even in ion implantation at a very low energy. This ion implantation method comprises the steps of carrying out preamorphization ion implantation for a semiconductor substra... | 06/24/2003 |
| 6562666 | Integrated circuits with reduced substrate capacitance Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction cap... | 05/13/2003 |
